Arteris Visa Sponsorship USA
Arteris is a semiconductor IP company specializing in network-on-chip interconnect technology, serving chip designers across the global technology industry. The company has a history of sponsoring H-1B and TN visas for specialized technical talent, making it a viable target for international engineers in semiconductor and hardware design.
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Get Access To All JobsVice President of Security Solutions Engineering
Location: Campell, CA
Arteris connects innovation. Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow.
What You’ll Do as a Vice President of Security Solutions Engineering at Arteris
Join our innovative team and help shape the future of semiconductor technology, specifically hardware security solutions. The Vice President of Engineering for Security Solutions operates as a core member of the company's senior leadership team, translating business objectives into executable engineering plans, establishing scalable operating mechanisms, and ensures that engineering commitments are credible, visible, and reliably delivered. Reporting to the senior VP of engineering, this leader builds and scales teams, mentoring leaders, clearly communicates technical strategy, translates complex concepts for non-technical stakeholders, ensures risks are identified early and managed decisively and aligns strategy across the organization. This role will lead a small growing team consisting of both individual contributors and one or more managers.
Key Responsibilities
- Technical Strategy & Architecture:
- Define and own the long‑term technical strategy for core hardware security engines, balancing innovation, scalability, and product quality.
- Review and challenge architectural and algorithmic decisions made by senior technical staff (architects, principal engineers) for high‑performance, memory‑efficient, and scalable analysis systems operating on very large designs.
-
Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness.
-
Execution & Delivery:
- Own delivery outcomes for software products, including correctness, runtime performance, memory footprint, and scalability.
- Ensure correctness, determinism, and debuggability of complex multi‑threaded and distributed systems.
- Drive predictable execution from research through productization in a commercial EDA environment.
-
Balance exploratory research with disciplined engineering practices.
-
Organization & Talent:
- Build, mentor, and retain a strong organization of senior engineers, architects, and engineering managers.
- Foster a culture of technical excellence, peer review, and evidence‑based decision making.
-
Develop future technical leaders within a mixed research and development engineering organization.
-
Cross‑Functional Leadership:
- Partner with management to translate customer direction and requests into an actionable R&D roadmap.
- Serve as the senior engineering interface to executive leadership on deep technical risks, tradeoffs, and investments.
- Communicate complex algorithmic issues clearly to non‑specialist stakeholders.
What You Bring
- At least 8 years of experience managing software teams (individual contributors and managers) that build and deliver complex C++ commercial technical applications.
- Demonstrated history of technical leadership involving setting product direction while also owning software (product) delivery and their outcomes (quality, timelines, reliability, user experience).
- Hands-on depth in at least one major EDA area (e.g., simulation, synthesis, formal verification, equivalence checking, static analysis), with the ability to evaluate architectural tradeoffs and algorithms.
- Strong grounding in algorithms and data structures for digital logic analysis and transformation.
- Practical understanding of SoC design and verification flows and how EDA tools are used in production environments.
- Track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that can operate on multi-billion gate designs.
- Executive-level communication skills with the ability to clearly articulate risks, tradeoffs, and outcomes to senior leadership and customers.
- Understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics.
- Expert programming and debug skills in modern C++.
- Proficiency working in Linux.
- Ability to build, lead, and mentor senior technical leaders (architects, principal engineers, engineering managers) while remaining deeply engaged in architectural and algorithmic design.
- Must exhibit a collaborative management style while maintaining strong communication and cross-functional leadership.
- Ability to operate effectively in a fast-paced, high-accountability environment with competing priorities.
- This position can be based in Campell CA, but highly qualified remote candidates located anywhere in the continental USA will be considered. Travel will be required for team and/or customer meetings.
- Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products.
- Familiarity with hardware security analysis or security oriented verification tools.
- Understanding of RTL/gate-level simulation and debugging.
- Experience in the implementation and verification of SoC designs.
Education Requirements
Bachelor’s degree in Computer Science or Electrical Engineering (MS/PhD preferred).
Estimated Base Salary:
$260,000 to $310,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Arteris
Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster.
With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.
Vice President of Security Solutions Engineering
Location: Campell, CA
Arteris connects innovation. Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow.
What You’ll Do as a Vice President of Security Solutions Engineering at Arteris
Join our innovative team and help shape the future of semiconductor technology, specifically hardware security solutions. The Vice President of Engineering for Security Solutions operates as a core member of the company's senior leadership team, translating business objectives into executable engineering plans, establishing scalable operating mechanisms, and ensures that engineering commitments are credible, visible, and reliably delivered. Reporting to the senior VP of engineering, this leader builds and scales teams, mentoring leaders, clearly communicates technical strategy, translates complex concepts for non-technical stakeholders, ensures risks are identified early and managed decisively and aligns strategy across the organization. This role will lead a small growing team consisting of both individual contributors and one or more managers.
Key Responsibilities
- Technical Strategy & Architecture:
- Define and own the long‑term technical strategy for core hardware security engines, balancing innovation, scalability, and product quality.
- Review and challenge architectural and algorithmic decisions made by senior technical staff (architects, principal engineers) for high‑performance, memory‑efficient, and scalable analysis systems operating on very large designs.
-
Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness.
-
Execution & Delivery:
- Own delivery outcomes for software products, including correctness, runtime performance, memory footprint, and scalability.
- Ensure correctness, determinism, and debuggability of complex multi‑threaded and distributed systems.
- Drive predictable execution from research through productization in a commercial EDA environment.
-
Balance exploratory research with disciplined engineering practices.
-
Organization & Talent:
- Build, mentor, and retain a strong organization of senior engineers, architects, and engineering managers.
- Foster a culture of technical excellence, peer review, and evidence‑based decision making.
-
Develop future technical leaders within a mixed research and development engineering organization.
-
Cross‑Functional Leadership:
- Partner with management to translate customer direction and requests into an actionable R&D roadmap.
- Serve as the senior engineering interface to executive leadership on deep technical risks, tradeoffs, and investments.
- Communicate complex algorithmic issues clearly to non‑specialist stakeholders.
What You Bring
- At least 8 years of experience managing software teams (individual contributors and managers) that build and deliver complex C++ commercial technical applications.
- Demonstrated history of technical leadership involving setting product direction while also owning software (product) delivery and their outcomes (quality, timelines, reliability, user experience).
- Hands-on depth in at least one major EDA area (e.g., simulation, synthesis, formal verification, equivalence checking, static analysis), with the ability to evaluate architectural tradeoffs and algorithms.
- Strong grounding in algorithms and data structures for digital logic analysis and transformation.
- Practical understanding of SoC design and verification flows and how EDA tools are used in production environments.
- Track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that can operate on multi-billion gate designs.
- Executive-level communication skills with the ability to clearly articulate risks, tradeoffs, and outcomes to senior leadership and customers.
- Understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics.
- Expert programming and debug skills in modern C++.
- Proficiency working in Linux.
- Ability to build, lead, and mentor senior technical leaders (architects, principal engineers, engineering managers) while remaining deeply engaged in architectural and algorithmic design.
- Must exhibit a collaborative management style while maintaining strong communication and cross-functional leadership.
- Ability to operate effectively in a fast-paced, high-accountability environment with competing priorities.
- This position can be based in Campell CA, but highly qualified remote candidates located anywhere in the continental USA will be considered. Travel will be required for team and/or customer meetings.
- Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products.
- Familiarity with hardware security analysis or security oriented verification tools.
- Understanding of RTL/gate-level simulation and debugging.
- Experience in the implementation and verification of SoC designs.
Education Requirements
Bachelor’s degree in Computer Science or Electrical Engineering (MS/PhD preferred).
Estimated Base Salary:
$260,000 to $310,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Arteris
Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster.
With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.
Job Roles at Arteris Companies
How to Get Visa Sponsorship in Arteris Visa Sponsorship USA
Target roles in semiconductor IP and hardware engineering
Arteris's core business is network-on-chip technology, so sponsorship activity concentrates in highly specialized engineering roles. Focus your application on positions where deep technical expertise in chip architecture or interconnect design aligns with your background.
Emphasize specialty occupation qualifications clearly
For semiconductor IP roles, Arteris needs to demonstrate your position qualifies as a specialty occupation. Lead with your degree in electrical engineering, computer engineering, or a directly related field to make the sponsorship case straightforward from the start.
Time your applications around H-1B filing windows
H-1B petitions must be filed by April 1 each year for an October 1 start date. If you're targeting Arteris, aim to secure an offer by January or February to give the company adequate time to prepare the petition and LCA.
Research open roles at verified sponsors before applying
Not every open role at a technology company comes with sponsorship. Migrate Mate surfaces verified sponsors so you can filter by real sponsorship history, helping you focus your job search on companies like Arteris that have an active track record.
Highlight niche technical skills that are hard to source domestically
Companies in specialized semiconductor IP are more motivated to sponsor when a candidate's skills are genuinely scarce in the local market. Expertise in NoC architecture, AMBA protocols, or advanced SoC design strengthens the business case Arteris makes to USCIS on your behalf.
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Get Access To All JobsFrequently Asked Questions
Does Arteris sponsor H-1B visas?
Yes, Arteris sponsors H-1B visas. The company operates in specialized semiconductor IP technology, where recruiting internationally is often necessary to find candidates with the right expertise. Sponsorship tends to focus on engineering and technical roles that directly support Arteris's network-on-chip product development, where a specific degree and skill set are required to qualify as a specialty occupation.
Which visa types does Arteris sponsor?
Arteris sponsors both H-1B and TN visas. The H-1B is the primary pathway for most international hires and requires entering the annual lottery unless you qualify for a cap-exempt category. The TN visa is available exclusively to Canadian and Mexican citizens under USMCA and is faster to obtain since it skips the lottery entirely. Confirming which visa applies to your situation before applying saves time for both you and the hiring team.
Which departments or roles at Arteris are most likely to receive visa sponsorship?
Sponsorship at Arteris is concentrated in technical engineering functions, particularly roles involving chip architecture, hardware design, and semiconductor IP development. Positions requiring deep expertise in network-on-chip interconnect technology, SoC integration, or AMBA protocols are strong candidates for sponsorship because the specialized skill set is difficult to source domestically. Software engineers working on EDA tools or verification flows related to Arteris's core products may also see sponsorship.
How do I find open visa-sponsored jobs at Arteris?
The most reliable approach is to use a job platform that filters by verified sponsorship history rather than relying on job listings that may not disclose sponsorship details upfront. Migrate Mate lets you search and filter roles specifically at companies like Arteris that have a documented track record of sponsoring international candidates, saving you from applying to roles where sponsorship isn't actually on the table.
How do I improve my chances of getting sponsored by Arteris?
Arteris operates in a highly specialized niche within the semiconductor industry, so the strongest applications come from candidates with directly relevant technical credentials. A degree in electrical engineering, computer engineering, or a closely related field is essential for H-1B specialty occupation qualification. Beyond credentials, demonstrating hands-on experience with the specific technologies Arteris builds around, such as interconnect IP or SoC architecture, makes the internal case for sponsorship much easier for the hiring team to advance.
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