Senior Level DFT Engineer Jobs
Senior level dft engineer jobs place experienced engineers in charge of test architecture decisions, silicon bring-up ownership, and the cross-functional teams that execute from design through validation. Openings concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, with a mix of on-site, remote, and hybrid settings, and employers like Broadcom, Apple, and Etched hiring at this level now.
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Showing 5 of 14+ Senior Level DFT Engineer jobs
Job Description:
DFT Engineer for ASIC/Chip level ATPG
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.
The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.
Responsibilities:
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
- Collaborate closely with STA and design integration engineers for timing and design closure.
- Generate, verify, and debug test vectors prior to tapeout release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and global test engineering/manufacturing teams.
- Work closely with IP DFT engineers and cross-functional stakeholders.
- Debug customer-returned parts (RMA) on ATE.
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
- Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
- Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, eDRAM, ROM)
- Experience with In-Field testing solutions a plus
- Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
- Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
- Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
- Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
- Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus
Education & Experience:
Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is USD 129,400.00 To USD 207,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Job Description:
DFT Engineer for ASIC/Chip level ATPG
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.
The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.
Responsibilities:
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
- Collaborate closely with STA and design integration engineers for timing and design closure.
- Generate, verify, and debug test vectors prior to tapeout release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and global test engineering/manufacturing teams.
- Work closely with IP DFT engineers and cross-functional stakeholders.
- Debug customer-returned parts (RMA) on ATE.
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
- Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
- Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, eDRAM, ROM)
- Experience with In-Field testing solutions a plus
- Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
- Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
- Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
- Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
- Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus
Education & Experience:
Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is USD 129,400.00 To USD 207,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Senior Level DFT Engineer Jobs: Frequently Asked Questions
How do I get a senior level dft engineer job?
Employers at this level look for engineers who have owned DFT flows end to end, not just contributed to them. Demonstrating hands-on experience with scan insertion, ATPG, boundary scan, and memory BIST across full tape-out cycles is table stakes. What gives candidates an edge is the ability to show architectural decisions they drove, design rule trade-offs they resolved, and junior engineers or contractors they have guided through execution.
Which companies hire senior level dft engineers?
Companies hiring senior level dft engineers right now include Broadcom, Apple, and Etched, based on current listings on Migrate Mate as of November 2026. Hiring at this level typically comes from semiconductor manufacturers, fabless chip design houses, and large-scale electronics companies with complex SoC or ASIC programs that require experienced engineers to own testability strategy.
Are there remote senior level dft engineer jobs?
Yes, though remote availability at this level varies by employer and project phase. About 14% of senior level dft engineer openings are remote or hybrid as of November 2026, with hybrid arrangements being most common given the lab access and cross-team collaboration these roles require during silicon bring-up and validation.
What makes a dft engineer role senior level?
A senior level dft engineer role is defined by scope and ownership rather than task completion. Senior engineers set DFT methodology for entire chips or product lines, make architectural trade-offs that affect yield and test time, and are accountable for tape-out readiness across multiple blocks. They are also expected to mentor engineers earlier in their careers, review peers' work, and drive alignment with design, verification, and manufacturing test teams.
Which industries hire the most senior level dft engineers?
Senior Level dft engineer roles concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, based on current listings on Migrate Mate as of November 2026. These sectors drive hiring at this level because their products depend on complex, high-volume silicon where test coverage, defect escape rates, and time-to-market directly affect revenue and product quality.