Senior Level Signal Integrity Engineer Jobs
Senior level signal integrity engineer jobs put experienced engineers in charge of high-speed design architecture, signal integrity methodology, and the cross-functional teams and projects that bring complex systems to completion. Openings are concentrated across on-site, remote, and hybrid settings in Electronics & Hardware, Technology & Software, and Telecommunications, with employers like Ampere Computing, Qualcomm, and Hewlett Packard Enterprise | HPE hiring at this level now.
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SUMMARY
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it! As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.
DESCRIPTION
In this highly visible role, your primary responsibilities will include:
- Define and architect consistent noise and STA analysis methodology, margins, and tool/version qualification strategy, and drive deployment across multiple projects with minimal oversight comprehensive EM/SEB/thermal methodologies and drive deployment across multiple advanced node designs with minimal oversight
- Own and drive flows and scripts for core gate-level noise and static timing analysis tools end to end, from constraint setup through sign-off, including automation, quality metrics, and continuous improvement
- Conduct deep root-cause analysis of noise violations and timing-path anomalies, increasingly accelerated with LLM-agent pipelines that auto-triage and classify failures by severity, aggressor pattern, or known failure signature
- Serve as the technical authority and primary point of contact for design and Physical Design teams on noise/timing constraint, flow, and closure issues, surfacing best practices
- Drive noise and STA methodology improvements, using AI coding agents (e.g., Claude Code, Copilot) to rapidly prototype and harden new analysis methodologies, margin models, and waiver-justification logic
- Build infrastructure for large-scale noise/timing report mining, QoR extraction, and visualization, including agent- or retrieval-backed natural-language query over report corpora
- Develop and support noise and timing ECO methodology and custom scripts for project tapeout
- Apply agentic diffing and summarization to accelerate tool and version qualification and flag regressions, while retaining human-in-the-loop judgment on signoff decisions and waivers
- Create documentation, guidelines, and specs, structured to also serve as grounding context for internal AI assistants supporting the team
- Mentor junior engineers on noise/STA analysis techniques and best practices
MINIMUM QUALIFICATIONS
- BS in Electrical Engineering, Computer Engineering, or related technical discipline and 10+ years of industry experience.
PREFERRED QUALIFICATIONS
- Hands-on experience with signal integrity analysis tools: Tempus, PrimeTime-SI, ETS/Celtic, or equivalent
- Solid understanding of STA fundamentals and PrimeTime specifics (Tcl coding, attributes, commands, reports)
- Strong Perl, Tcl, and/or Python scripting skills and a systematic debugging approach
- Working knowledge of crosstalk, OCV effects, margins, constraints, aggressor selection, and correlation basics
- BS or MS in a technical discipline
- Ability to plan and execute tool/methodology evaluations, qualifying a new tool or tool version in a systematic, repeatable manner
- Exposure to transistor-level analysis and SPICE simulation
- Expertise in AI/ML-driven and agentic-workflow innovation for CAD and noise/timing flows (LLM-based triage, debug-copilot workflows, agent-based report mining)
- Experience wrapping existing Perl/Tcl flow scripts as callable tools within an agent framework for natural-language-driven flow operations
- Familiarity with noise and timing ECO techniques and implementation
- Excellent communication and presentation skills; ability to coordinate initiatives with design teams and CAD groups with little to no oversight
COMPENSATION
- Base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
Apple believes accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
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Senior Level Signal Integrity Engineer Jobs: Frequently Asked Questions
How do I get a senior level signal integrity engineer job?
Employers at this level expect demonstrated ownership of full signal integrity workflows, from pre-layout simulation through post-silicon validation. Candidates who stand out bring experience defining design rules, mentoring junior engineers, and presenting findings to cross-functional stakeholders. Proficiency with tools like HyperLynx, Cadence, or Ansys, combined with a portfolio of shipped high-speed products, is what moves applications forward.
Which companies hire senior level signal integrity engineers?
Companies hiring senior level signal integrity engineers right now include Ampere Computing, Qualcomm, and Hewlett Packard Enterprise | HPE, based on current listings on Migrate Mate as of November 2026. Hiring at this level tends to concentrate in semiconductor manufacturers, defense electronics contractors, and large consumer electronics firms with active high-speed PCB or chip development programs.
Are there remote senior level signal integrity engineer jobs?
Yes, though many roles require at least some on-site access to lab equipment and hardware. About 43% of senior level signal integrity engineer openings are remote or hybrid as of November 2026, reflecting the hands-on nature of the discipline. Fully remote positions typically exist at companies with distributed hardware teams and strong simulation-focused workflows.
What makes a signal integrity engineer role senior level?
Senior level signal integrity engineer roles go beyond executing tasks to owning methodology. That means setting design constraints for entire product lines, leading root-cause analysis on complex signal integrity failures, defining simulation and validation processes for the team, and providing technical mentorship to mid and junior engineers. Scope, independence, and cross-functional influence are the defining differences from mid-level positions.
Which industries hire the most senior level signal integrity engineers?
Senior Level signal integrity engineer roles concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, based on current listings on Migrate Mate as of November 2026. These sectors drive demand because they develop high-speed digital systems where signal integrity directly affects product performance, reliability, and regulatory compliance at scale.