Design Architect Visa Sponsorship Jobs in California
Design architect visa sponsorship jobs in California put you at the center of some of the most ambitious built-environment work in the country. Firms like Gensler, HOK, and Skidmore, Owings and Merrill maintain major California studios, while tech campuses in the Bay Area and mixed-use developments across Los Angeles drive sustained demand for licensed design architects.
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Get Access To All JobsDate posted 11/03/2026
Category Engineering
Hire Type Employee
Job ID 19496
Base Salary Range $0-$0
Remote Eligible No
Date Posted 11/03/2026
We Are
At Synopsys, we drive the innovations shaping the Era of Pervasive Intelligence, enabling everything from autonomous systems to advanced AI compute. Our leadership in chip design, verification, and IP integration powers the world’s most demanding silicon. Join us to build industry-leading SerDes IP that defines next-generation connectivity.
You Are
You are a Principal-level analog design leader with deep expertise in high-speed SerDes and silicon-proven analog macros. You operate at the architecture and system boundary, translating standards and product requirements into robust, scalable circuit and layout implementations. You lead through technical influence by setting direction, driving alignment across teams, and mentoring engineers to deliver high-quality outcomes. You are recognized for sound judgment in power, area, and performance trade-offs, disciplined verification methodology, and the ability to resolve complex cross-domain issues spanning analog, digital calibration and control, and physical design. You communicate clearly with internal stakeholders and customers, presenting data-driven decisions and guiding technical reviews with authority and clarity.
What You’ll Be Doing
- Own macro-level architecture, design, and implementation of critical analog circuits for SerDes IP across TX, RX, and clock paths.
- Interpret SerDes standards and system architecture to define detailed analog specifications, budgets, and design targets including jitter, noise, linearity, settling, latency, power, and area.
- Drive top-level architecture trade-offs and define scalable circuit platforms reusable across product variants and process nodes.
- Lead and track technical execution across multiple sub-block owners, identify risk early, remove blockers, and ensure alignment to schedule and product goals.
- Define clear interfaces between analog macros and digital calibration, adaptation, and control, partnering with RTL and firmware teams to co-define algorithms and observability hooks.
- Define and enforce robust verification strategies using advanced SPICE and simulator capabilities including corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, PVT sweeps, and reliability checks.
- Champion best practices in modeling including Verilog-A behavioral models to accelerate system validation and improve correlation between block and top-level results.
- Drive silicon correlation plans by defining key measurements, mapping results to simulations, and feeding learnings back into design improvements.
- Provide technical oversight to physical layout to minimize parasitics, coupling, device stress, and process variation sensitivity, ensuring reliability and ESD are addressed from the start.
- Guide FinFET layout strategies for mismatch, symmetry, routing, shielding, EM and IR, and high-speed interconnect integrity.
- Present architecture rationale, simulation results, and risk assessments in peer and customer reviews, responding to technical questions with data-backed clarity.
- Consult on electrical characterization and test strategy for SerDes IP macros, influencing DFT and bring-up hooks and lab debug workflows.
- Mentor junior and mid-level engineers, setting a high technical bar for design quality, documentation, and review rigor.
- Contribute to team capability through reusable collateral, methodology improvements, and onboarding practices as the organization scales.
The Impact You Will Have
- Set technical direction for key SerDes analog macros, enabling best-in-class performance and reliability for next-generation standards.
- Improve predictability and quality through stronger verification methodology, correlation strategy, and design reuse.
- Elevate cross-functional execution across analog, layout, and digital teams, reducing integration risk and accelerating tapeout readiness.
- Provide technical leadership in customer engagements, strengthening Synopsys’ reputation for silicon-proven IP.
- Develop engineering talent through mentorship and technical leadership, strengthening long-term organizational capability.
What You’ll Need
- PhD with 10+ years, or MSc with 12+ years of SerDes or high-speed analog design experience with multiple silicon successes.
- Demonstrated ability to lead macro-level architecture and deliver complex analog IP through tapeout and silicon validation.
- Deep transistor-level design expertise and strong CMOS and FinFET fundamentals.
- Silicon-proven experience implementing circuits for TX, RX, and clock paths within SerDes architectures.
- In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
- Advanced skills guiding FinFET CMOS layouts to minimize parasitics and local device mismatches.
- Awareness of ESD and reliability issues including circuit techniques and layout strategies.
- Proficiency with EDA tools for schematic entry, physical layout, and design verification.
- Experience with SPICE simulators for detailed circuit analysis.
- Familiarity with analog behavioral modeling and simulation control using Verilog-A.
- Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.
- Clear potential to lead a team in the near future as the team continues to grow.
The Team
You will join a multidisciplinary team of analog, digital, and mixed-signal engineers developing industry-leading SerDes IP solutions. The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products. Collaboration, mentorship, and technical innovation are central to the culture, and your leadership will have a direct impact on both product success and team growth.
Diversity and Accommodation
Synopsys Canada ULC values the diversity of our workforce and is committed to providing access and opportunity to individuals with disabilities. Reasonable accommodation is available throughout the recruitment and employment process. If you require accommodation, please contact hr-help-canada@synopsys.com.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can
Date posted 11/03/2026
Category Engineering
Hire Type Employee
Job ID 19496
Base Salary Range $0-$0
Remote Eligible No
Date Posted 11/03/2026
We Are
At Synopsys, we drive the innovations shaping the Era of Pervasive Intelligence, enabling everything from autonomous systems to advanced AI compute. Our leadership in chip design, verification, and IP integration powers the world’s most demanding silicon. Join us to build industry-leading SerDes IP that defines next-generation connectivity.
You Are
You are a Principal-level analog design leader with deep expertise in high-speed SerDes and silicon-proven analog macros. You operate at the architecture and system boundary, translating standards and product requirements into robust, scalable circuit and layout implementations. You lead through technical influence by setting direction, driving alignment across teams, and mentoring engineers to deliver high-quality outcomes. You are recognized for sound judgment in power, area, and performance trade-offs, disciplined verification methodology, and the ability to resolve complex cross-domain issues spanning analog, digital calibration and control, and physical design. You communicate clearly with internal stakeholders and customers, presenting data-driven decisions and guiding technical reviews with authority and clarity.
What You’ll Be Doing
- Own macro-level architecture, design, and implementation of critical analog circuits for SerDes IP across TX, RX, and clock paths.
- Interpret SerDes standards and system architecture to define detailed analog specifications, budgets, and design targets including jitter, noise, linearity, settling, latency, power, and area.
- Drive top-level architecture trade-offs and define scalable circuit platforms reusable across product variants and process nodes.
- Lead and track technical execution across multiple sub-block owners, identify risk early, remove blockers, and ensure alignment to schedule and product goals.
- Define clear interfaces between analog macros and digital calibration, adaptation, and control, partnering with RTL and firmware teams to co-define algorithms and observability hooks.
- Define and enforce robust verification strategies using advanced SPICE and simulator capabilities including corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, PVT sweeps, and reliability checks.
- Champion best practices in modeling including Verilog-A behavioral models to accelerate system validation and improve correlation between block and top-level results.
- Drive silicon correlation plans by defining key measurements, mapping results to simulations, and feeding learnings back into design improvements.
- Provide technical oversight to physical layout to minimize parasitics, coupling, device stress, and process variation sensitivity, ensuring reliability and ESD are addressed from the start.
- Guide FinFET layout strategies for mismatch, symmetry, routing, shielding, EM and IR, and high-speed interconnect integrity.
- Present architecture rationale, simulation results, and risk assessments in peer and customer reviews, responding to technical questions with data-backed clarity.
- Consult on electrical characterization and test strategy for SerDes IP macros, influencing DFT and bring-up hooks and lab debug workflows.
- Mentor junior and mid-level engineers, setting a high technical bar for design quality, documentation, and review rigor.
- Contribute to team capability through reusable collateral, methodology improvements, and onboarding practices as the organization scales.
The Impact You Will Have
- Set technical direction for key SerDes analog macros, enabling best-in-class performance and reliability for next-generation standards.
- Improve predictability and quality through stronger verification methodology, correlation strategy, and design reuse.
- Elevate cross-functional execution across analog, layout, and digital teams, reducing integration risk and accelerating tapeout readiness.
- Provide technical leadership in customer engagements, strengthening Synopsys’ reputation for silicon-proven IP.
- Develop engineering talent through mentorship and technical leadership, strengthening long-term organizational capability.
What You’ll Need
- PhD with 10+ years, or MSc with 12+ years of SerDes or high-speed analog design experience with multiple silicon successes.
- Demonstrated ability to lead macro-level architecture and deliver complex analog IP through tapeout and silicon validation.
- Deep transistor-level design expertise and strong CMOS and FinFET fundamentals.
- Silicon-proven experience implementing circuits for TX, RX, and clock paths within SerDes architectures.
- In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
- Advanced skills guiding FinFET CMOS layouts to minimize parasitics and local device mismatches.
- Awareness of ESD and reliability issues including circuit techniques and layout strategies.
- Proficiency with EDA tools for schematic entry, physical layout, and design verification.
- Experience with SPICE simulators for detailed circuit analysis.
- Familiarity with analog behavioral modeling and simulation control using Verilog-A.
- Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.
- Clear potential to lead a team in the near future as the team continues to grow.
The Team
You will join a multidisciplinary team of analog, digital, and mixed-signal engineers developing industry-leading SerDes IP solutions. The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products. Collaboration, mentorship, and technical innovation are central to the culture, and your leadership will have a direct impact on both product success and team growth.
Diversity and Accommodation
Synopsys Canada ULC values the diversity of our workforce and is committed to providing access and opportunity to individuals with disabilities. Reasonable accommodation is available throughout the recruitment and employment process. If you require accommodation, please contact hr-help-canada@synopsys.com.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can
Design Architect Job Roles in California
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Search Design Architect Jobs in CaliforniaDesign Architect Jobs in California: Frequently Asked Questions
Which companies in California sponsor visas for design architects?
Large architecture and design firms with established California offices are the most consistent sponsors for design architects. Gensler's San Francisco and Los Angeles studios, HOK, Skidmore Owings and Merrill, HKS, and Perkins and Will all have documented visa sponsorship histories. Corporate real estate departments at major technology companies in the Bay Area also sponsor design architects for in-house roles overseeing campus and workplace projects.
What visa types are available for design architects seeking sponsorship in California?
Design architects in California most commonly pursue H-1B visa sponsorship, which requires a specialty occupation tied to a relevant bachelor's degree and is subject to an annual cap and selection process. Canadian and Mexican citizens holding an architecture degree or license may qualify for TN visa status under USMCA, which covers the Architect profession. Employer-sponsored EB-2 or EB-3 green cards are available for longer-term permanent residence pathways, typically after initial nonimmigrant status is established.
How to find design architect visa sponsorship jobs in California?
Migrate Mate lists California design architect roles specifically at employers with verified visa sponsorship history, so you can focus on firms already familiar with the sponsorship process rather than applying broadly and hoping. Filtering by city lets you target San Francisco, Los Angeles, or San Diego studios directly. Because design architect roles require a specialty occupation degree match, reviewing each listing's stated qualifications before applying helps confirm your credentials align with what the sponsoring firm will need to demonstrate to USCIS.
Which California cities have the most design architect visa sponsorship jobs?
San Francisco and Los Angeles account for the largest share of sponsored design architect positions in California. San Francisco's dense commercial and tech-sector development sustains demand at both large firms and boutique studios. Los Angeles draws significant work in entertainment facilities, mixed-use developments, and civic projects. San Diego has a smaller but active market tied to biotech campuses and hospitality construction, while Silicon Valley offices of major firms sponsor architects for technology workplace projects.
Are there state-specific factors that affect design architect sponsorship in California?
California requires architects to hold a license from the California Architects Board to practice independently, though many sponsored roles are at the design or project architect level where licensure is in progress. The state's volume of large-scale public, commercial, and residential development creates consistent firm hiring. California's university architecture programs at UC Berkeley, UCLA, and Cal Poly produce pipelines into local firms, some of which extend sponsorship to international graduates completing OPT after earning their degrees.
What is the prevailing wage for sponsored design architect jobs in California?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.