DFT Engineer Visa Sponsorship Jobs in California
DFT engineer visa sponsorship jobs in California are concentrated in Silicon Valley, with major semiconductor companies like Intel, Qualcomm, Apple, NVIDIA, and Broadcom actively sponsoring foreign nationals. San Jose, Santa Clara, and San Diego anchor most hiring activity, driven by California's dense integrated circuit design ecosystem and proximity to leading electrical engineering programs.
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Get Access To All JobsINTRODUCTION
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up.
The candidate will support various phases of SoC DFT-related activities for Broadcom APD’s designs, including test insertion, pattern generation, coverage improvement, and basic silicon debug. The role involves collaborating with cross-functional teams, including Physical Design and STA engineers.
BASIC QUALIFICATIONS
- Basic coding/scripting skills in TCL, Perl, Python, C++, or Verilog are expected.
Responsibilities
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
- Working closely with I/P DFT engineers & other stakeholders
- Debugging customer returned parts on the ATE
- Innovating newer DFT solutions to solve testability problems in 3nm & beyond
- Automating DFT & Test Vector Generation flows
PREFERRED QUALIFICATIONS
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Logic BIST design and debug experience
- Well-versed in ATPG vector generation, simulation, debug (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
- The ability to work in a multi-disciplined, cross-department environment
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
- Excellent problem solving, debug, root cause analysis and communication skills
- Experience working on ATE is a plus
EDUCATION & EXPERIENCE
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 10+ years of experience.
COMPENSATION AND BENEFITS
- The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
LOCATION
Location: San Jose, California
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
INTRODUCTION
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up.
The candidate will support various phases of SoC DFT-related activities for Broadcom APD’s designs, including test insertion, pattern generation, coverage improvement, and basic silicon debug. The role involves collaborating with cross-functional teams, including Physical Design and STA engineers.
BASIC QUALIFICATIONS
- Basic coding/scripting skills in TCL, Perl, Python, C++, or Verilog are expected.
Responsibilities
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
- Working closely with I/P DFT engineers & other stakeholders
- Debugging customer returned parts on the ATE
- Innovating newer DFT solutions to solve testability problems in 3nm & beyond
- Automating DFT & Test Vector Generation flows
PREFERRED QUALIFICATIONS
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Logic BIST design and debug experience
- Well-versed in ATPG vector generation, simulation, debug (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
- The ability to work in a multi-disciplined, cross-department environment
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
- Excellent problem solving, debug, root cause analysis and communication skills
- Experience working on ATE is a plus
EDUCATION & EXPERIENCE
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 10+ years of experience.
COMPENSATION AND BENEFITS
- The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
LOCATION
Location: San Jose, California
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
DFT Engineer Job Roles in California
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Search DFT Engineer Jobs in CaliforniaDFT Engineer Jobs in California: Frequently Asked Questions
Which companies sponsor visas for DFT engineers in California?
California's semiconductor companies are among the most active sponsors for DFT engineers. Intel, Qualcomm, Apple, NVIDIA, Broadcom, Marvell, AMD, and Synopsys have consistent histories of sponsoring H-1B visa petitions for design-for-test roles. Smaller fabless chip companies in Silicon Valley and San Diego also sponsor regularly, particularly for engineers with expertise in ATPG, scan insertion, or boundary-scan methodologies.
What visa types realistically fit DFT engineer roles in California?
DFT engineering is a specialty occupation requiring a bachelor's degree in electrical engineering, computer engineering, or a closely related field, making H-1B the most common path. The employer files a Labor Condition Application and I-129 petition. E-3 visa applies to Australian citizens, H-1B1 visa to Chilean and Singaporean nationals. Canadian and Mexican citizens with the required engineering degree may qualify under TN visa status. EB-2 and EB-3 green card sponsorship is also common at large semiconductor firms.
Which cities in California have the most DFT engineer sponsorship jobs?
San Jose and Santa Clara lead by volume, sitting at the heart of Silicon Valley's semiconductor corridor. San Diego is a strong secondary market due to Qualcomm's headquarters and a cluster of wireless chip companies. Folsom hosts Intel's design operations. Smaller but active hiring hubs include Milpitas, Sunnyvale, and Santa Rosa, each home to established semiconductor or EDA companies with ongoing DFT staffing needs.
How to find dft engineer visa sponsorship jobs in California?
Migrate Mate lists California DFT engineer roles specifically at employers with verified visa sponsorship history, so you can focus on companies that have already sponsored similar positions rather than applying broadly and asking later. Search by city to target Silicon Valley, San Diego, or Sacramento-area opportunities. Filtering to DFT-specific job titles helps surface roles in scan design, ATPG, and test automation where sponsorship is most active.
Are there state-specific factors that affect DFT engineer visa sponsorship in California?
California's dense concentration of semiconductor and EDA companies means prevailing wage levels for DFT engineers are set high relative to most other states, since DOL bases wages on regional data. Employers here are experienced with H-1B sponsorship processes and often have dedicated immigration teams. University pipelines from UC Berkeley, UCLA, UC San Diego, and Stanford feed international graduate talent directly into California's chip design industry, keeping sponsorship demand steady.
What is the prevailing wage for sponsored dft engineer jobs in California?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.