SoC Design Engineer Visa Sponsorship Jobs in Oregon
SoC design engineer visa sponsorship jobs in Oregon are concentrated in the Portland–Hillsboro corridor, home to Intel's largest U.S. campus, along with semiconductor firms like Lattice Semiconductor and Synopsys. The region's deep chip design ecosystem, fed partly by Oregon State University graduates, creates steady demand for sponsored SoC engineers with RTL, verification, and physical design expertise.
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Get Access To All JobsSUMMARY
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
DESCRIPTION
- As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- You will lead schedules and support cross-functional engineering efforts.
- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
MINIMUM QUALIFICATIONS
- BS degree with 0 years of relevant industry experience.
PREFERRED QUALIFICATIONS
- Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
- Understands RTL to GDS physical design flow
- Scripting skills to debug flow related issues and make enhancements as appropriate
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
- Layout design background and experience a plus
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
SUMMARY
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
DESCRIPTION
- As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- You will lead schedules and support cross-functional engineering efforts.
- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
MINIMUM QUALIFICATIONS
- BS degree with 0 years of relevant industry experience.
PREFERRED QUALIFICATIONS
- Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
- Understands RTL to GDS physical design flow
- Scripting skills to debug flow related issues and make enhancements as appropriate
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
- Layout design background and experience a plus
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
SoC Design Engineer Job Roles in Oregon
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Search SoC Design Engineer Jobs in OregonSoC Design Engineer Jobs in Oregon: Frequently Asked Questions
Which companies sponsor visas for SoC design engineers in Oregon?
Intel is the dominant sponsor in Oregon, with its Hillsboro campus serving as a major hub for chip design and verification work. Lattice Semiconductor, headquartered in Hillsboro, also sponsors engineers for SoC and FPGA roles. Synopsys maintains an Oregon presence supporting EDA and silicon design teams. Smaller fabless startups in the Portland area have also filed Labor Condition Applications for SoC design positions.
Which visa types realistically fit SoC design engineer roles in Oregon?
The H-1B visa is the most common path, as SoC design engineering qualifies as a specialty occupation requiring a bachelor's degree in electrical engineering, computer engineering, or a closely related field. Canadian and Mexican nationals may qualify for TN visa status under the USMCA Engineer category. Australian nationals can pursue the E-3 visa. H-1B1 visa status is available to Chilean and Singaporean nationals. F-1 students may use OPT or STEM OPT given the STEM-designated degree requirement for this role.
Which cities in Oregon have the most SoC design engineer sponsorship jobs?
Hillsboro is by far the leading city, driven by Intel's massive campus and the broader Washington County semiconductor cluster. Portland hosts additional design teams from companies like Synopsys and various EDA tool vendors. Corvallis, home to Oregon State University's electrical and computer engineering programs, occasionally surfaces roles from research-adjacent employers. Outside these three cities, SoC sponsorship activity in Oregon drops significantly.
How to find soc design engineer visa sponsorship jobs in Oregon?
Migrate Mate lists Oregon SoC design engineer roles specifically from employers with verified visa sponsorship history, so you can focus on companies that have actually filed for similar positions. Filtering by role and state surfaces active opportunities in the Hillsboro–Portland corridor without sifting through postings from employers with no sponsorship track record. Creating an alert for SoC design engineer roles in Oregon helps you stay current as new sponsored positions are added.
Are there state-specific factors that affect SoC design engineer visa sponsorship in Oregon?
Oregon's semiconductor industry is unusually concentrated compared to most states, meaning a relatively small number of large employers account for a high share of sponsorship activity. Intel's Hillsboro operations have historically been one of the largest filers of H-1B Labor Condition Applications nationally for engineering roles. Oregon State University and Portland State University supply local talent pipelines, but demand routinely exceeds domestic supply, which supports continued employer willingness to sponsor qualified international SoC engineers.
What is the prevailing wage for sponsored soc design engineer jobs in Oregon?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.