Senior Level ASIC Design Verification Engineer Jobs
Senior level asic design verification engineer jobs place experienced engineers in charge of verification architecture, methodology decisions, and the cross-functional teams driving silicon to tapeout. Openings are concentrated across Electronics & Hardware, Telecommunications, and Technology & Software, with a mix of on-site, hybrid, and remote roles available, and employers like Nokia, Cisco, and Axiado hiring at this level now.
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Job Description:
We are looking for a detail-oriented and experienced VLSI ASIC Verification Engineer to join our silicon engineering team. In this role, you will own the functional verification of complex digital blocks and subsystems. You will build scalable, reusable UVM testbenches, drive constrained-random and assertion-based verification, and ensure zero-bug tape-outs.
Key Responsibilities
- Verification Planning: Analyze micro-architectural specifications to create comprehensive verification plans, trace requirements, and identify edge/corner cases.
- Testbench Development: Design and build modular, reusable verification environments and testbenches using SystemVerilog and Universal Verification Methodology (UVM).
- Stimulus & Scoreboarding: Develop constrained-random stimulus, functional coverage models, scoreboards, and reference models.
- Assertions & Debug: Write SystemVerilog Assertions (SVA) to catch design violations early, run simulations, debug waveforms, and root-cause RTL-to-testbench mismatches.
- Coverage Closure: Drive functional and code coverage to 100% closure prior to tape-out.
- Automation & Regressions: Maintain automated regression suites using scripting languages like Python, Perl, or Tcl.
Required Qualifications
- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Experience: minimum 8 years of hands-on experience in ASIC, SoC, or IP design verification.
- Core Methodologies: Deep proficiency in SystemVerilog and UVM architectures (agents, drivers, monitors, scoreboards, virtual sequences).
- Bus Protocols: Solid working knowledge of AMBA protocols (AXI, AHB, APB) and memory/DMA controllers.
- Verification Techniques: Proven track record in constrained-random verification, functional coverage closure, and assertion-based verification (SVA).
- EDA Tools: Hands-on experience with industry-standard simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium/Incisive, Mentor/Siemens Questa, or Verdi).
- Scripting: Strong scripting skills (Ex: Python, Tcl, or Perl) for build-flow automation and regression management.
Preferred Qualifications
- Familiarity with formal verification tools and techniques.
- Processor Architectures: Hands-on verification experience with RISC-V, ARM, or x86 core or subsystem architectures.
- CPU Pipeline & Core Verification: Deep understanding of processor pipelines, branch prediction, out-of-order execution, superscalar designs, and execution units (ALU/FPU).
- Memory Subsystem Expertise: Familiarity with verifying complex memory hierarchies, including L1/L2 caches, cache coherency protocols (AMBA CHI / ACE), MMUs, and virtual memory management.
- Exposure to high-speed interfaces or external protocols (DDR, PCIe, NVMe, SATA, or SAS).
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job.
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
We are looking for a detail-oriented and experienced VLSI ASIC Verification Engineer to join our silicon engineering team. In this role, you will own the functional verification of complex digital blocks and subsystems. You will build scalable, reusable UVM testbenches, drive constrained-random and assertion-based verification, and ensure zero-bug tape-outs.
Key Responsibilities
- Verification Planning: Analyze micro-architectural specifications to create comprehensive verification plans, trace requirements, and identify edge/corner cases.
- Testbench Development: Design and build modular, reusable verification environments and testbenches using SystemVerilog and Universal Verification Methodology (UVM).
- Stimulus & Scoreboarding: Develop constrained-random stimulus, functional coverage models, scoreboards, and reference models.
- Assertions & Debug: Write SystemVerilog Assertions (SVA) to catch design violations early, run simulations, debug waveforms, and root-cause RTL-to-testbench mismatches.
- Coverage Closure: Drive functional and code coverage to 100% closure prior to tape-out.
- Automation & Regressions: Maintain automated regression suites using scripting languages like Python, Perl, or Tcl.
Required Qualifications
- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Experience: minimum 8 years of hands-on experience in ASIC, SoC, or IP design verification.
- Core Methodologies: Deep proficiency in SystemVerilog and UVM architectures (agents, drivers, monitors, scoreboards, virtual sequences).
- Bus Protocols: Solid working knowledge of AMBA protocols (AXI, AHB, APB) and memory/DMA controllers.
- Verification Techniques: Proven track record in constrained-random verification, functional coverage closure, and assertion-based verification (SVA).
- EDA Tools: Hands-on experience with industry-standard simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium/Incisive, Mentor/Siemens Questa, or Verdi).
- Scripting: Strong scripting skills (Ex: Python, Tcl, or Perl) for build-flow automation and regression management.
Preferred Qualifications
- Familiarity with formal verification tools and techniques.
- Processor Architectures: Hands-on verification experience with RISC-V, ARM, or x86 core or subsystem architectures.
- CPU Pipeline & Core Verification: Deep understanding of processor pipelines, branch prediction, out-of-order execution, superscalar designs, and execution units (ALU/FPU).
- Memory Subsystem Expertise: Familiarity with verifying complex memory hierarchies, including L1/L2 caches, cache coherency protocols (AMBA CHI / ACE), MMUs, and virtual memory management.
- Exposure to high-speed interfaces or external protocols (DDR, PCIe, NVMe, SATA, or SAS).
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Senior Level ASIC Design Verification Engineer Jobs: Frequently Asked Questions
How do I get a senior level asic design verification engineer job?
Employers at this level expect ownership of the full verification lifecycle, from planning coverage models and writing complex UVM testbenches to closing on sign-off. Candidates who stand out demonstrate independent technical judgment, the ability to mentor junior engineers, and a history of driving verification closure on complex IPs or subsystems. Deep expertise in formal verification, assertion-based verification, or specific protocol domains gives a strong edge.
Which companies hire senior level asic design verification engineers?
Companies hiring senior level asic design verification engineers right now include Nokia, Cisco, and Axiado, based on current listings on Migrate Mate as of November 2026. Hiring at this level is led by semiconductor design houses, fabless chip companies, and large technology firms building custom silicon for compute, networking, and mobile applications.
Are there remote senior level asic design verification engineer jobs?
Yes, though availability varies by employer and project stage. About 25% of senior level asic design verification engineer openings are remote or hybrid as of November 2026, reflecting the simulation-heavy and tool-driven nature of verification work. Roles tied to lab bringup, emulation platforms, or close collaboration with design teams are more likely to require on-site presence.
What makes a asic design verification engineer role senior level?
A senior level role goes beyond executing assigned tasks to owning a verification domain end to end, defining the testbench architecture, setting coverage targets, and making methodology calls that affect the entire project. Senior engineers are expected to review others' work, unblock junior team members, interface with design and architecture teams, and represent verification quality in milestone reviews without day-to-day oversight.
Which industries hire the most senior level asic design verification engineers?
Senior Level asic design verification engineer roles concentrate in Electronics & Hardware, Telecommunications, and Technology & Software, based on current listings on Migrate Mate as of November 2026. These sectors drive demand because they invest heavily in custom or semi-custom silicon development, requiring experienced verification engineers who can manage complexity and deliver reliable sign-off on tightly scheduled tape-out timelines.