Design Lead Jobs in Sunnyvale, CA
Design Lead jobs in Sunnyvale, California are open across the metro, with employers like Google, Intuitive (Intuitive Surgical), and Apple hiring at every experience level. Find a role that fits below and apply directly.
Find Design Lead JobsOverview
Open roles43
Top employerGoogle
Work type96% On-site
Top credentialBachelor's
Companies hiring11
Showing 5 of 43+ Design Lead jobs
Physical Design Technical Lead, ASIC, TPU
We won't show you this job again
Added 3d ago
Google
Physical Design Technical Lead, ASIC, TPU
Sunnyvale, California
Added 3d ago
Technical Lead Manager, Machine Learning, Memory Subsystem Design
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Added 4d ago
Google
Technical Lead Manager, Machine Learning, Memory Subsystem Design
Sunnyvale, California
Added 4d ago
Physical Design Lead, Static Timing Analysis
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Added 2w ago
Google
Physical Design Lead, Static Timing Analysis
Sunnyvale, California
Added 2w ago
ASIC Design Verification Technical Lead, TPU
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Added 3w ago
Google
ASIC Design Verification Technical Lead, TPU
Sunnyvale, California
Added 3w ago
Technical Lead, Custom Digital Circuit Design, Mixed Signal
We won't show you this job again
Added 1mo ago
Google
Technical Lead, Custom Digital Circuit Design, Mixed Signal
Sunnyvale, California
Added 1mo ago
Added 3d ago
Physical Design Technical Lead, ASIC, TPU
Google·Sunnyvale, California
Job functions:
$192k - $279k/yr
10+ yrs exp.
Bachelor's
Full Time
10,000+ employees
Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
Google
Physical Design Technical Lead, ASIC, TPU
Sunnyvale, California
Added 3d ago10,000+ employees
Job functions:
$192k - $279k/yr
10+ yrs exp.
Bachelor's
Full Time
Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
See All 43 Design Lead Jobs in Sunnyvale
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Find Design Lead JobsDesign Lead Job Market in Sunnyvale
Who's Hiring
- Google22
- Intuitive (Intuitive Surgical)7
- Apple4
- Nokia2
- Amazon2
Top Industries Hiring
- Technology & Software35
- Artificial Intelligence22
- Electronics & Hardware6
- Retail2
- Science & Research2
Design Lead Jobs in Sunnyvale: Frequently Asked Questions
How many design lead jobs are there in Sunnyvale?
There are 43+ design lead openings in Sunnyvale, California on Migrate Mate as of June 2026. New positions post regularly as Sunnyvale employers hire.
Which companies hire design leads in Sunnyvale?
Companies currently hiring design leads in Sunnyvale include Google, Intuitive (Intuitive Surgical), and Apple, per current listings on Migrate Mate as of June 2026.
Are there remote design lead jobs in Sunnyvale?
Yes. About 4% of design lead openings tied to Sunnyvale are remote or hybrid as of June 2026. The rest are on-site roles based in and around Sunnyvale.
Which industries hire the most design leads in Sunnyvale?
Most design lead openings in Sunnyvale sit in Technology & Software, Artificial Intelligence, and Electronics & Hardware, per current listings on Migrate Mate as of June 2026.
Related Jobs in California
See All 43 Design Lead Jobs in Sunnyvale
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