Mid Level Design Verification Jobs
Mid level design verification jobs go to engineers ready to own verification plans end to end, mentor junior team members, and drive coverage decisions with limited oversight. Roles run across on-site, remote, and hybrid settings in Technology & Software, Electronics & Hardware, and Artificial Intelligence, with employers like Etched, Google, and NVIDIA hiring at this level now.
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SUMMARY
Did you know that Apple is hiring analog & mixed signal verification engineers? We are looking for engineers that are enthusiastic to find bugs! You have the opportunity to work with a creative team to craft test plans and enable production-quality first silicon. As a member of the analog and mixed signal verification team, you will be working with specialists for full-chip verification of the state of the art mixed-signal systems used in Apple’s world-leading products!
DESCRIPTION
In this role, you will be responsible for ensuring high quality silicon for IC chips and IPs. Daily work involves verification of mixed signal IC designs using a combination of analog circuits and RTL in the same simulation. Responsibilities include all phases of pre-silicon verification from early discussions with architects, reviewing specifications, writing verification plans, running simulations, triaging issues, and reviewing results with the team.
- Develop detailed test and coverage plans based on IC specifications.
- Completion of verification plans from beginning to end: test bench and environment bring-up, regressions, failure debug, and tape-out.
- Develop verification methodology suitable for the IP, ensuring scalability and portability.
- Develop verification environment, including stimuli, checkers, assertions, trackers, and coverage.
- Sign-off mixed signal designs in preparation for tapeout.
MINIMUM QUALIFICATIONS
- BS and a minimum of 3 years of relevant industry experience.
PREFERRED QUALIFICATIONS
- Ability to verify analog/mixed-signal designs in a collaborative team environment.
- Proficient in hardware descriptive languages: Verilog, System-Verilog, and/or Verilog-AMS code.
- Familiarity with authoring analog assertion checks to catch bugs.
- Capability to identify failure mechanisms and review verification results in analog IC designs.
- Ability to write test plans, present results, and communicate clearly with multi-functional teams.
- Comfortable with running simulations through compute clusters while optimizing simulation and wall time.
- Understanding of both power management and related auxiliary circuitry: switching converters, linear converters, reference circuitry, bandgaps, data converters, and/or clock generators.
- Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, coverage collection, gate level simulations.
- Experience developing scalable and portable test benches.
- A background that includes scripting or programming languages is preferred. These include, but are not limited to, TCL, Skill, Python, and/or PERL.
- Your familiarity with analog behavioral models is also a plus.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
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Mid Level Design Verification Jobs: Frequently Asked Questions
How do I get a mid level design verification job?
Position yourself around ownership, not just task completion. Highlight projects where you defined the verification plan, closed coverage gaps independently, or caught critical bugs before tape-out. Emphasize familiarity with UVM or SystemVerilog testbench development, experience with coverage closure, and any cross-functional collaboration with design or DFT teams. Concrete metrics, such as coverage percentages achieved or bugs caught by stage, make applications stand out at this level.
Which companies hire mid level design verifications?
Companies hiring mid level design verifications right now include Etched, Google, and NVIDIA, based on current listings on Migrate Mate as of November 2026. Hiring at this level covers semiconductor companies, fabless chip designers, and electronics manufacturers that need engineers who can run verification flows independently rather than under close supervision.
Are there remote mid level design verification jobs?
Yes, though on-site roles remain common in this discipline given the lab and tool access many teams require. About 13% of mid level design verification openings are remote or hybrid as of November 2026, concentrated largely at companies with distributed engineering teams or cloud-based EDA tool setups. Filtering by work setting on Migrate Mate shows which specific openings offer flexibility.
How do I move up to a mid level design verification role?
The path from entry level to mid level in design verification is built on demonstrable ownership. Early in your career, focus on mastering testbench development, understanding coverage methodology, and contributing to bug triage. Over time, take initiative on defining test plans for new blocks, mentor peers informally, and document the measurable impact of your work. Consistent depth in one or two areas, such as formal verification or emulation, accelerates the transition.
Which industries hire the most mid level design verifications?
Mid Level design verification roles concentrate in Technology & Software, Electronics & Hardware, and Artificial Intelligence, based on current listings on Migrate Mate as of November 2026. These sectors drive hiring because they depend on complex, high-volume silicon development where robust pre-silicon verification directly reduces costly respins and accelerates time to market.