Digital Verification Engineer Jobs
Digital Verification Engineer jobs are open across semiconductor, automotive, aerospace, and consumer electronics, from new-grad to principal and staff levels, with specializations in functional verification, formal verification, and UVM-based testbench development. See the openings below and apply to the ones that match your experience.
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Principal Scientist, Cleaning Verification Center of Excellence Strategy Lead, Pharmaceutical Analysis and Digital Technologies
The Pharmaceutical Analysis and Digital Technologies (PADT) team has an opening for a Principal Scientist to serve as Strategy Lead for our Cleaning Verification Center of Excellence (CoE), based in Rahway, NJ.
In this role, the Principal Scientist will define and lead the strategy for the Cleaning Verification CoE, establishing harmonized, science- and risk-based approaches to cleaning verification across all modalities in our clinical portfolio, including small molecule (e.g., oral solid dosage forms and sterile liquids) and large molecule programs. The Strategy Lead will drive the development, validation, and lifecycle management of cleaning verification methods and practices, ensuring cGMP compliance, operational excellence, and a sustained state of inspection readiness. The Principal Scientist should be engaged with regulatory and industry trends, including health-based exposure limits (HBELs), and have thorough working knowledge of cGMPs, ICH, and relevant FDA and global health authority expectations for cleaning verification and validation.
In addition, the Strategy Lead will partner with Analytical leadership, extended leadership teams, and cross-functional stakeholders in Process Engineering, Clinical Manufacturing, and Quality and to identify and advance key departmental strategic and cultural initiatives. As the recognized subject matter expert, the Principal Scientist will mentor scientists and build cleaning verification capability across the organization through training, knowledge sharing, and coaching. The role will also be responsible for proactive resource planning, risk assessment strategies, and continuous improvement of CoE processes, standards, and tools.
Primary Responsibilities
Essential knowledge and responsibilities include:
- Technical expertise in analytical methodologies applied to cleaning verification for both small and large molecules, such as liquid chromatography, total organic carbon (TOC), spectroscopy, and conductivity, including swab/rinse sampling and recovery studies.
- Define and execute the Cleaning Verification CoE strategy and roadmap, including harmonized standards, best practices, and governance across programs and sites.
- Lead the development, validation, and transfer of cleaning verification methods to enable on-time, right first-time equipment release for clinical manufacture of drug substance and drug product.
- Partner with Process Engineering, Clinical Manufacturing, and Quality to establish science- and risk-based cleaning acceptance limits across small and large molecule modalities (e.g., HBEL-based carryover calculations).
- Provide technical and compliance oversight on cleaning-related lab investigations and deviations including root cause analysis and identification of robust corrective and preventative actions.
- Review and approval of cleaning verification data, protocols, technical reports, and SOPs.
- Serve as the cleaning verification subject matter expert during internal and external compliance audits and regulatory inspections.
- Drive operational excellence, innovation, and process improvements, including evaluation and implementation of new analytical technologies and digital tools.
- Technical mentorship and development of scientists, building cleaning verification capability across the organization.
- Cross-functional leadership and influence, including working with senior management to drive departmental strategic and cultural initiatives.
- PhD Degree in Analytical Chemistry, Biochemistry, Pharmaceutical Sciences or related fields with at least 7 years of pharmaceutical industry experience​.
- Master’s Degree in Analytical Chemistry, Biochemistry, Pharmaceutical Sciences or related fields with at least 10 years of pharmaceutical industry experience.
- Bachelor’s Degree in Analytical Chemistry, Biochemistry, Pharmaceutical Sciences or related fields with at least 12 years of pharmaceutical industry experience. ​
- Proven technical leadership in analytical cleaning verification and/or validation, ideally in a GMP setting; experience with both small and large molecules preferred.
- Track record of shaping and delivering strategy and influencing without direct authority in a matrixed organization.
- In-depth knowledge of cGMP, ICH, FDA, and global health authority expectations for cleaning verification and validation.
- Excellent scientific communication skills and a creative, collaborative approach.
- Strong coaching and interpersonal skills, with the ability to work effectively in cross-functional teams.
Required Skills:
Analytical Chemistry, Analytical Method Development, Assay Development, Bioanalytical Analysis, Biochemistry, Cleaning Validations, Clinical Judgment, Drug Launches, Liquid Chromatography (LC), Matrix Leadership, Method Validation, Pharmaceutical Industry, Pharmaceutical Sciences, Regulatory Inspections, Small Molecules
Preferred Skills:
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Our company is committed to inclusion, ensuring that candidates can engage in a hiring process that exhibits their true capabilities. Please click here if you need an accommodation during the application or hiring process.
As an Equal Employment Opportunity Employer, we provide equal opportunities to all employees and applicants for employment and prohibit discrimination on the basis of race, color, age, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability status, or other applicable legally protected characteristics. As a federal contractor, we comply with all affirmative action requirements for protected veterans and individuals with disabilities. For more information about personal rights under the U.S. Equal Opportunity Employment laws, visit:
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We are proud to be a company that embraces the value of bringing together, talented, and committed people with diverse experiences, perspectives, skills and backgrounds. The fastest way to breakthrough innovation is when people with diverse ideas, broad experiences, backgrounds, and skills come together in an inclusive environment. We encourage our colleagues to respectfully challenge one another’s thinking and approach problems collectively.
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The primary location for this posting is:
USA - New Jersey - Rahway
Where required by law, the compensation range for this role is provided below.
The salary range for the primary location of this role is:
$156,900.00 - $247,000.00
This range reflects the Company's reasonable expectation of the base salary applicable to this role at the time of posting. An employee’s position within the salary range will be based on several factors including, but not limited to relevant education, qualifications, certifications, experience, skills, geographic location, government requirements, and business or organizational needs. The successful candidate will be eligible for annual bonus and long-term incentive, if applicable.
We offer a comprehensive package of benefits. Available benefits include medical, dental, vision healthcare and other insurance benefits (for employee and family), retirement benefits, including 401(k), paid holidays, vacation, and compassionate and sick days. More information about benefits is available at https://jobs.merck.com/us/en/compensation-and-benefits.
Additional location(s): Please note the salary range above applies to the Primary Location of the position. Where a role has other listed locations, different compensation guidelines may apply. You may find the salary ranges for additional locations below. If the salary range is not listed for the location you are applying to, our Talent Acquisition team will provide further information to you relevant to your location.
Additional location(s) Compensation Information:
San Francisco Residents Only: We will consider qualified applicants with arrest and conviction records for employment in compliance with the San Francisco Fair Chance Ordinance
Los Angeles Residents Only: We will consider for employment all qualified applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles’ Fair Chance Initiative for Hiring Ordinance
Search Firm Representatives Please Read Carefully
Merck & Co., Inc., Rahway, NJ, USA, also known as Merck Sharp & Dohme LLC, Rahway, NJ, USA, does not accept unsolicited assistance from search firms for employment opportunities. All CVs / resumes submitted by search firms to any employee at our company without a valid written search agreement in place for this position will be deemed the sole property of our company. No fee will be paid in the event a candidate is hired by our company as a result of an agency referral where no pre-existing agreement is in place. Where agency agreements are in place, introductions are position specific. Please, no phone calls or emails.
Employee Status:
Regular
Relocation:
VISA Sponsorship:
Travel Requirements:
Flexible Work Arrangements:
Not Applicable
Shift:
Valid Driving License:
Hazardous Material(s):
Job Posting End Date:
12/11/2026*A job posting is effective until 11:59:59PM on the day BEFORE the listed job posting end date. Please ensure you apply to a job posting no later than the day BEFORE the job posting end date.
Requisition ID: R425993
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Find JobsDigital Verification Engineer Job Market
Who's Hiring



Top Industries Hiring
- Technology & Software
- Electronics & Hardware
What Employers Look For
The qualifications that appear most often in digital verification engineer jobs.
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and the Universal Verification Methodology
- Experience writing constraint-random testbenches and functional coverage models
- Familiarity with simulation tools such as VCS, Questa, or Xcelium
- Understanding of formal verification techniques and tools like JasperGold
- Experience with scripting languages such as Python or Perl for verification automation
Tips for Your Digital Verification Engineer Job Search
Tailor your resume to methodology keywords
Hiring managers scan for specific verification methodologies before reading anything else. Call out UVM, SystemVerilog assertions, formal verification tools, and coverage-driven verification explicitly in your skills section and each relevant role description.
Highlight closure metrics in your bullet points
Vague claims about testing experience lose out to candidates who show results. Quantify code coverage percentages achieved, the number of bugs caught pre-silicon, or regression suite size to give reviewers concrete evidence of your contributions.
Apply early to roles that fit
Migrate Mate lists digital verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by design abstraction level
Job titles vary widely but the work differs significantly between block-level, subsystem, and full-chip verification. Read each posting carefully to identify which abstraction layer is the focus so you target roles that match your actual depth of experience.
Prepare for tool-specific technical screens
Many interviews include live coding or debugging exercises in SystemVerilog or a constraint-random environment. Practice writing self-checking testbenches, defining coverage groups, and debugging simulation waveforms before you get on a call with an engineering team.
Negotiate scope and rotation opportunities upfront
Verification teams vary from project-focused to platform-wide roles. Asking in the final interview stage about the rotation policy, tape-out cycle length, and design team collaboration structure signals seniority and helps you evaluate whether the role builds toward your career goals.
Digital Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most digital verification engineers?
Infineon Technologies, NVIDIA, and TikTok are hiring the most digital verification engineers right now, with openings concentrated in California, Kentucky, and Texas, based on current listings on Migrate Mate as of November 2026. Semiconductor fabless companies and automotive chip divisions tend to post the highest volumes of these roles.
How many digital verification engineer jobs are remote?
About 0% of digital verification engineer openings are fully remote or hybrid as of November 2026, though the share varies by specialization. Formal verification and software-driven testbench roles tend to be more remote-friendly, while positions tied to lab hardware bring-up or on-site simulation infrastructure are more likely to require in-person work.
How do you become a digital verification engineer?
Start with a degree in electrical engineering, computer engineering, or computer science, then build hands-on skills in SystemVerilog and UVM through coursework, personal projects, or open-source verification environments. Internships or co-ops at semiconductor or automotive chip companies give you exposure to real regression flows and coverage closure. Many engineers enter through ASIC or FPGA design roles and transition into verification by volunteering for testbench work on their teams.
Can you get a digital verification engineer job with little experience?
Yes, entry-level positions exist, particularly at companies with structured new-graduate programs in their verification departments. The strongest candidates without industry experience demonstrate UVM testbench projects from coursework or personal repositories, familiarity with at least one major simulator, and an understanding of coverage-driven verification concepts. Focusing your applications on companies that actively recruit from universities with strong computer engineering programs improves your odds significantly.
What does the digital verification engineer interview process look like?
Most processes start with a recruiter screen followed by a technical phone interview covering SystemVerilog syntax, testbench architecture, and coverage methodology basics. A take-home or live coding exercise requiring you to write a constrained-random testbench or debug a failing simulation is common at the midpoint. Final rounds typically involve a panel of senior verification engineers asking about coverage closure strategies, bug-hunting experience, and how you approach a new design block.
Where can I find and apply to digital verification engineer jobs?
You can find and apply to digital verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Search for roles that fit your specialization and experience level, then apply directly to each listing that matches what you're looking for.
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