Senior Level Formal Verification Engineer Jobs
Senior level formal verification engineer jobs place experienced engineers at the forefront of silicon correctness, owning verification methodology, driving tool strategy, and leading the teams responsible for tape-out confidence. Openings concentrate across Technology & Software, Electronics & Hardware, and Telecommunications, with a mix of on-site, hybrid, and remote positions available, and employers like Qualcomm, Google, and NVIDIA hiring at this level now.
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Open roles9
Top stateCalifornia
Top employerQualcomm
Top citySan Diego, CA
Work type88% On-site
Top industryTechnology
Showing 5 of 9+ Senior Level Formal Verification Engineer jobs
ASIC Formal Verification Engineer, TPU Compute
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Added 5mo ago
Google
ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California
Added 5mo ago
Senior Formal Verification Engineer
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Added 6mo ago
NVIDIA
Senior Formal Verification Engineer
Florida
Added 6mo ago
Distinguished Engineer, Formal Verification
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Added 6mo ago
Astera Labs
Distinguished Engineer, Formal Verification
San Jose, California
Added 6mo ago
Senior Staff Formal Verification Engineer
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Added 10mo ago
Qualcomm
Senior Staff Formal Verification Engineer
San Diego, California
Added 10mo ago
Senior Staff Formal Verification Engineer
We won't show you this job again
Added 10mo ago
Qualcomm
Senior Staff Formal Verification Engineer
Santa Clara, California
Added 10mo ago
Added 5mo ago
ASIC Formal Verification Engineer, TPU Compute
Google·Sunnyvale, California
Job functions:
$163k - $237k/yr
8+ yrs exp.
Bachelor's degree in electrical engineering
Full Time
10,000+ employees
Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in silicon development or ASIC/SoC design.
- Experience with SystemVerilog Assertions (SVA) and formal verification methods.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
- 10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal).
- Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking.
- Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers.
- Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.As an ASIC Formal Verification Engineer, you'll contribute formal verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
- Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
- Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
- Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
- Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.
Google
ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California
Added 5mo ago10,000+ employees
Job functions:
$163k - $237k/yr
8+ yrs exp.
Bachelor's degree in electrical engineering
Full Time
Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in silicon development or ASIC/SoC design.
- Experience with SystemVerilog Assertions (SVA) and formal verification methods.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
- 10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal).
- Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking.
- Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers.
- Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.As an ASIC Formal Verification Engineer, you'll contribute formal verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
- Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
- Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
- Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
- Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.
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Senior Level Formal Verification Engineer Jobs: Frequently Asked Questions
How do I get a senior level formal verification engineer job?
Employers at this level expect deep hands-on fluency with tools like JasperGold or Synopsys VC Formal, plus a portfolio of complex block or subsystem sign-offs you personally owned. What gives candidates an edge is the ability to define verification plans from scratch, mentor junior engineers, and communicate risk clearly to design and program leadership. Narrow your focus to roles that match your strongest protocol or domain expertise.
Which companies hire senior level formal verification engineers?
Companies hiring senior level formal verification engineers right now include Qualcomm, Google, and NVIDIA, based on current listings on Migrate Mate as of November 2026. Hiring at this level is led by semiconductor design houses, fabless chip companies, and large technology firms with dedicated silicon or ASIC teams.
Are there remote senior level formal verification engineer jobs?
Yes, though remote availability varies by employer and project phase. About 13% of senior level formal verification engineer openings are remote or hybrid as of November 2026, reflecting the tool-driven nature of formal work. Companies with established remote engineering cultures tend to offer the most flexibility at this seniority level.
What makes a formal verification engineer role senior level?
Senior roles are defined by scope and ownership. Where a mid-level engineer executes a verification plan on an assigned block, a senior engineer authors the plan, selects the methodology, and is accountable for signoff quality across one or more complex IPs. Senior engineers also mentor junior team members, engage cross-functionally with design and architecture, and are expected to resolve ambiguous coverage or convergence problems independently.
Which industries hire the most senior level formal verification engineers?
Senior Level formal verification engineer roles concentrate in Technology & Software, Electronics & Hardware, and Telecommunications, based on current listings on Migrate Mate as of November 2026. These sectors drive demand because they produce high-complexity digital designs where the cost of a logic bug in silicon is prohibitive, making rigorous formal property checking a non-negotiable part of the development process.