J-1 Visa Design Verification Jobs
Design Verification roles in the U.S. are accessible to international professionals through J-1 visa sponsorship under the Trainee or Research Scholar category, depending on your experience level. A U.S. Department of State-designated sponsor organization issues your DS-2019, while the hardware or semiconductor company serves as your host employer.
See All Design Verification JobsOverview
Showing 5 of 6+ Design Verification jobs
Have you applied for this role?
Have you applied for this role?
Have you applied for this role?
Have you applied for this role?
Have you applied for this role?
See all 6+ Design Verification jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Verification roles.
Get Access To All JobsINTRODUCTION
Altera is seeking a highly motivated Graduate Intern to join our FPGA Digital Design and Verification team. This internship provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for graduate students eager to grow their expertise in SystemVerilog, UVM-based verification, and digital design methodologies.
You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.
ROLE AND RESPONSIBILITIES
- Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
- Create self-checking testbenches, constrained-random tests, and functional coverage models
- Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
- Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
- Assist in debugging RTL and verification failures, working closely with design engineers
- Verify common communication protocols (e.g., UART, SPI) and custom interconnects
- Contribute to documentation of verification plans, test strategies, and results
- Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components
BASIC QUALIFICATIONS
- Currently pursuing a Graduate Degree in Computer or Electrical Engineering or related field
- Strong foundation in Digital Logic Design and Computer Architecture
- Proficiency in SystemVerilog and Verilog
- Knowledge of UVM, functional coverage, constrained random verification, and assertions
- Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
- Familiarity with Linux-based development environments
- Ability to debug simulation issues and analyze waveforms effectively
PREFERRED QUALIFICATIONS
- Hands-on project experience with UVM-based verification environments
- Experience verifying communication protocols (UART, SPI, AXI preferred)
- Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
- Knowledge of SVA or formal verification concepts
- Programming or scripting experience in Python, Perl, Tcl, or C
- Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads
COMPENSATION
- Salary Range: $95K - $100K USD
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
JOB TYPE
Student / Intern (Fixed Term)
SHIFT
Shift 1 (United States of America)
LOCATION
Primary Location: San Jose, California, United States
POSTING STATEMENT
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
INTRODUCTION
Altera is seeking a highly motivated Graduate Intern to join our FPGA Digital Design and Verification team. This internship provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for graduate students eager to grow their expertise in SystemVerilog, UVM-based verification, and digital design methodologies.
You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.
ROLE AND RESPONSIBILITIES
- Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
- Create self-checking testbenches, constrained-random tests, and functional coverage models
- Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
- Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
- Assist in debugging RTL and verification failures, working closely with design engineers
- Verify common communication protocols (e.g., UART, SPI) and custom interconnects
- Contribute to documentation of verification plans, test strategies, and results
- Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components
BASIC QUALIFICATIONS
- Currently pursuing a Graduate Degree in Computer or Electrical Engineering or related field
- Strong foundation in Digital Logic Design and Computer Architecture
- Proficiency in SystemVerilog and Verilog
- Knowledge of UVM, functional coverage, constrained random verification, and assertions
- Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
- Familiarity with Linux-based development environments
- Ability to debug simulation issues and analyze waveforms effectively
PREFERRED QUALIFICATIONS
- Hands-on project experience with UVM-based verification environments
- Experience verifying communication protocols (UART, SPI, AXI preferred)
- Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
- Knowledge of SVA or formal verification concepts
- Programming or scripting experience in Python, Perl, Tcl, or C
- Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads
COMPENSATION
- Salary Range: $95K - $100K USD
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
JOB TYPE
Student / Intern (Fixed Term)
SHIFT
Shift 1 (United States of America)
LOCATION
Primary Location: San Jose, California, United States
POSTING STATEMENT
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
See all 6+ Design Verification jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Verification roles.
Get Access To All JobsTips for Finding J-1 Visa Sponsorship in Design Verification
Frame your credentials around functional competencies
Translate your verification experience into U.S.-recognized skill sets: formal verification, simulation, emulation, and coverage closure. Designated sponsors assess whether your background maps to a structured training plan, so document specific tools like SystemVerilog, UVM, or assertion-based verification before applying.
Distinguish Trainee from Research Scholar eligibility early
The Trainee category suits professionals within five years of graduation with prior industry exposure. Research Scholar applies if your Design Verification work involves original investigation at a university or research institute. Applying under the wrong category delays your DS-2019 and can void a host employer's offer.
Target host employers with structured engineering rotations
Semiconductor and EDA companies running formal internship or rotational programs already have the training-plan infrastructure that designated sponsors require. Search Migrate Mate to identify U.S. employers actively posting Design Verification roles that align with J-1 exchange visitor timelines and program structures.
Negotiate training plan terms before signing an offer
Your DS-2019 is tied to a specific training plan co-signed by the host employer and the designated sponsor. Confirm that the job description matches your approved objectives before accepting. Scope changes after issuance require an amendment, which adds processing time and can affect your program start date.
Check whether your home country triggers the two-year requirement
Many Design Verification professionals come from countries on the Exchange Visitor Skills List, triggering the two-year home residency requirement under INA section 212(e). USCIS and the U.S. Department of State determine this based on your J-1 category and funding source, not your employer's preference.
Verify host employer compliance capacity before committing
Your host employer must sign a formal agreement with the designated sponsor, maintain adequate liability insurance, and assign a responsible officer. Ask the recruiter whether the company has hosted J-1 exchange visitors before and whether they have an existing relationship with a State Department-designated sponsor organization.
Design Verification jobs are hiring across the US. Find yours.
Find Design Verification JobsDesign Verification J-1 Visa: Frequently Asked Questions
Which J-1 program category fits a Design Verification professional?
Most Design Verification candidates qualify under the Trainee category if they have a degree in electrical engineering, computer engineering, or a related field and fewer than five years of post-graduation industry experience. Those conducting original research at a university or national laboratory may qualify under the Research Scholar category instead. The host employer's environment and your specific activities determine which applies.
Who actually sponsors the J-1 visa for a Design Verification role?
The visa sponsor is a U.S. Department of State-designated organization such as Cultural Vistas or AIPT, not your employer. The designated sponsor issues the DS-2019 form, approves the training plan, and monitors program compliance. The semiconductor or hardware company where you work is the host employer and signs a hosting agreement with that sponsor organization.
How do I find U.S. employers open to hosting J-1 Design Verification professionals?
Migrate Mate lists U.S. employers and open Design Verification roles that align with J-1 exchange visitor program requirements. Not every employer is familiar with the J-1 host-employer process, so targeting companies that already run structured engineering training programs or academic partnerships is an effective filter when searching.
Does the two-year home residency requirement affect Design Verification professionals?
It can. If your J-1 is funded by your home government, if your occupation appears on the U.S. Department of State's Exchange Visitor Skills List, or if your program is government-financed, you may be subject to the INA section 212(e) two-year requirement. USCIS adjudicates waiver requests if you later seek H-1B or green card status without returning home first.
Can a Design Verification J-1 trainee switch host employers mid-program?
Changing host employers mid-program requires the designated sponsor to approve an amendment to your DS-2019 and training plan. The new host employer must independently satisfy the sponsor's hosting requirements and sign a new agreement. Your J-1 status does not automatically transfer, and a gap between hosts can jeopardize your lawful exchange visitor status.
See which Design Verification employers are hiring and sponsoring visas right now.
Search Design Verification Jobs