Senior Level Layout Designer Jobs
Senior level layout designer jobs put experienced designers in charge of visual systems, production standards, and the creative direction that shapes how projects come to life. Openings are spread across on-site, hybrid, and remote settings in Electronics & Hardware, Telecommunications, and Staffing & Recruiting, with employers like Ampere Computing, Nokia, and Etched hiring at this level now.
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Showing 5 of 8+ Senior Level Layout Designer jobs
INTRODUCTION
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
ROLE AND RESPONSIBILITIES
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
BASIC QUALIFICATIONS
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
PREFERRED QUALIFICATIONS
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
WHAT WE OFFER
- The chance to play a foundational role at a high-growth semiconductor start-up
- Exposure to a wide variety of cross functional teams
- A collaborative, international team culture where ideas and initiative are valued
- The opportunity to grow alongside Celero as we scale and shape the future of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
INTRODUCTION
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
ROLE AND RESPONSIBILITIES
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
BASIC QUALIFICATIONS
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
PREFERRED QUALIFICATIONS
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
WHAT WE OFFER
- The chance to play a foundational role at a high-growth semiconductor start-up
- Exposure to a wide variety of cross functional teams
- A collaborative, international team culture where ideas and initiative are valued
- The opportunity to grow alongside Celero as we scale and shape the future of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
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Who's Hiring
Top Industries Hiring
- Electronics & Hardware
- Telecommunications
- Staffing & Recruiting
- Technology & Software
Senior Level Layout Designer Jobs: Frequently Asked Questions
How do I get a senior level layout designer job?
Senior level layout designer roles go to candidates who can demonstrate ownership of complex projects from concept through final production. Employers at this level look for a portfolio that shows systems thinking, not just executional skill, along with evidence of mentoring junior designers or leading cross-functional creative reviews. Specialization in a particular medium, such as editorial, packaging, or digital publishing, adds a meaningful edge.
Which companies hire senior level layout designers?
Companies hiring senior level layout designers right now include Ampere Computing, Nokia, and Etched, based on current listings on Migrate Mate as of November 2026. At this level, hiring tends to come from established organizations with dedicated creative, marketing, or editorial departments that need experienced designers to own output quality and guide production workflows.
Are there remote senior level layout designer jobs?
Yes, though availability varies by employer and industry. About 57% of senior level layout designer openings are remote or hybrid as of November 2026, reflecting broader flexibility across creative and publishing roles. Organizations with distributed teams or agency-style structures tend to offer the most remote options at the senior level.
What makes a layout designer role senior level?
Senior level layout designer roles are defined by scope, autonomy, and responsibility for outcomes. These positions involve owning the visual and production standards for entire projects or product lines, making decisions without close supervision, and mentoring less experienced designers. The technical depth required is higher, often including mastery of grid systems, typography, and multi-channel production, combined with the ability to defend creative decisions to stakeholders.
Which industries hire the most senior level layout designers?
Senior Level layout designer roles concentrate in Electronics & Hardware, Telecommunications, and Staffing & Recruiting, based on current listings on Migrate Mate as of November 2026. These sectors drive hiring because they produce high volumes of designed content across print, digital, and brand channels, requiring experienced designers who can maintain quality and consistency at scale.