Senior Level Lead System Architect Jobs

We are hiring in Sunnyvale, CA or Mississauga, ON

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary and detail-oriented architect, passionate about pushing the boundaries of high-speed serial-link transceivers. With deep expertise spanning analog circuit design, DSP, and communications theory, you see the SerDes as a complete system. You dissect complex standards and architectural requirements and translate them into robust, scalable designs, balancing power, area, and performance trade-offs across the analog and digital boundary. Your experience spans both the theoretical and practical aspects of SerDes development, from system modeling in MATLAB/Simulink to silicon-proven analog macros and lab correlation.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes. With proven leadership skills, you thrive in multidisciplinary environments alongside analog, digital, and hardware engineers, and you are eager to mentor the next generation of engineers. As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence. You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you are excited to make a lasting impact at Synopsys.

What You’ll Be Doing:

• Own the architecture of SerDes IP for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+), from system definition through analog macro implementation.
• Interpret SerDes standards and develop system models and link budgets that translate into detailed analog and DSP specifications.
• Lead the design of analog macro-level circuits across the TX, RX, and clock paths, optimizing for power, area, and performance targets.
• Run comprehensive system and circuit simulations to verify and sign off design performance across multiple protocols and channels.
• Design and propose calibration, adaptation, and control algorithms, collaborating closely with digital RTL engineers on their implementation.
• Oversee physical layout to minimize parasitics, device stress, and process variation impacts.
• Correlate simulated performance with silicon measurements and contribute to lab testing and electrical characterization.
• Track and review the technical progress of sub-block owners and junior engineers.
• Present technical insights for peer and customer reviews, and support customers on system-level issues.
• Document design features, methodologies, and test plans for internal and customer use.

The Impact You Will Have:

• Drive innovation and quality in Synopsys’ industry-leading SerDes IP for wireline and optical applications.
• Accelerate bleeding-edge silicon IP, enabling next-generation connectivity standards.
• Bridge system architecture and circuit implementation, ensuring designs are optimized end-to-end.
• Contribute to the success of global customers by delivering robust, silicon-proven IP that reduces time-to-market.
• Enhance cross-functional collaboration across system, analog, digital, layout, and lab teams.
• Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.
• Influence the direction of advanced design, modeling, and verification methodologies.

What You’ll Need:

• PhD with 10+ years, or MSc with 12+ years of SerDes/high-speed analog and mixed-signal design experience.
• Silicon-proven, transistor-level design experience in TX, RX, and clock paths within SerDes architectures.
• In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers/deserializers, VCOs, phase interpolators, PLLs, ADCs, and DACs.
• Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
• Strong experience modeling systems in MATLAB/Simulink and analyzing link budgets for PAM4 serial links.
• Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Proficiency with EDA tools and SPICE simulators, plus hands-on lab testing of high-speed serial links.
• Programming experience in Verilog-A, SystemVerilog, C, TCL, and Python.

Who You Are:

• Innovative, analytical thinker with exceptional problem-solving skills.
• Collaborative leader who thrives in a multidisciplinary environment.
• Effective communicator, able to translate complex concepts for diverse audiences.
• Detail-oriented and methodical in approach.
• Adaptable and eager to learn, keeping pace with evolving technologies.
• Mentor and role model for junior engineers.
• Customer-focused and proactive in driving project outcomes.

The Team You’ll Be A Part Of:

You will join a dynamic, multidisciplinary R&D team of system architects and analog, digital, mixed-signal, and hardware engineers dedicated to developing industry-leading SerDes IP for wireline and optical applications. The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products. Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.