ASIC Engineer Jobs
ASIC Engineer jobs are open across semiconductor, consumer electronics, aerospace, and defense, from new-grad to principal and staff levels, with specializations in RTL design, physical design, and verification. See the openings below and apply to the ones that match your experience.
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Meet the Team
Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!
Welcome to the Electrical Post-Silicon Validation Team at Cisco! Our group offers an outstanding combination of a startup culture with the benefits of working for the leading networking company in the world. You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification and quality of the ASIC throughout its lifecycle.
Operating at the forefront of technology, we work with cutting-edge, high-speed, and power-hungry devices. Our small, but highly influential team thrives in this challenging environment, leveraging our expertise to impact the future of networking technology. With a commitment to excellence and a passion for transformative technology, we are shaping the future of high-performance Networking devices and delivering unparalleled value in every project we undertake. Join us and be a part of a team where professionalism meets impact.
Your Impact
We are seeking a versatile Senior Hardware Engineer to join the team. Your involvement across multiple stages of the product lifecycle offers a unique opportunity to engage with a broad range of technical fields. In this highly visible role, you will play a key part in ensuring our products perform reliably, from pre-silicon validation and post-silicon bring-up through manufacturing support, field issue resolution, and ongoing quality and reliability improvements.
- Lead and participate in failure analysis efforts, determining contributing factors and corrective actions.
- Lead activities aiming at improving product performance, yield, and reliability.
- Define, and refine post silicon validation plans covering functionality, performance characterization, and reliability.
- Capture, analyze, and interpret device performance, waveforms, eye diagrams, jitter, BER, PDN measurements, power supply stability and noise.
- Validate system-level behavior using dedicated built in tests and real-world networking workloads.
- Contribute to the chip screening test and observability software library (Python, C++).
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and 6+ years of relevant experience, or Master's degree in Electrical Engineering, Computer Engineering, or related field and 3+ years of relevant experience, or PhD in Electrical Engineering, Computer Engineering, or related field and 1+ years of relevant related work experience.
- Relevant experience with Electrical post-silicon validation (Vmin, leakage, PVT characterization, …), SoC failure analysis, Power and signal integrity, High speed mixed-signal design, DFT, SRAM design, Firmware (FW) developmentand/or integration.
- Software development experience with Python, C++ or similar language.
- Experience in driving SoC failure analysis efforts.
- Experience in brining up complex SoC.
- Experience with electrical diagnostics and measurement equipment (Oscilloscopes, VNA, BERT, logic analyzers...).
- Experience in high-speed physical interfaces.
- Experience in design for test (DFT).
- Experience in physical and/or logic design.
- Experience in memory design and MBIST.
- Understanding of networking fundamentals and protocols..
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$167,700.00 - $282,000.00
Non-Metro New York state& Washington state:
$149,100.00 - $250,900.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
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Find ASIC Engineer JobsASIC Engineer Job Market
Who's Hiring
- Meta32

- Apple26

- Cisco24

- NVIDIA24

- Lockheed Martin19

Top Industries Hiring
- Technology & Software16
- Electronics & Hardware14
- Telecommunications7
- Aerospace & Defense2
- Artificial Intelligence2
What Employers Look For
The qualifications that appear most often in ASIC engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with industry EDA tools such as Cadence, Synopsys, or Mentor Graphics
- Hands-on experience with at least one full ASIC design and tapeout cycle
- Knowledge of static timing analysis, DFT methodology, and low-power design techniques
- Familiarity with scripting languages such as Python or Tcl for design automation
Tips for Your ASIC Engineer Job Search
Tailor your resume to each tapeout
List every tapeout you've contributed to by node, foundry, and your specific role in the flow. Hiring managers scan for TSMC 7nm or Samsung 5nm experience before they read anything else on your resume, so front-load those details.
Highlight tool proficiency with version context
Name the exact EDA tools you've used and pair them with the flow stage: synthesis, place-and-route, timing closure, or signoff. Generic mentions of Cadence or Synopsys mean less than specifying Genus for synthesis or Innovus for P&R.
Apply early to roles that fit
Migrate Mate lists asic engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target postings by design phase
Filter openings by whether the team is pre-tapeout, in physical implementation, or in post-silicon validation. Your strongest experience maps to one phase, so applying to roles in that stage raises your interview conversion rate significantly.
Prepare a timing closure case study for interviews
Most technical screens for asic engineer roles include a live or take-home timing problem. Walk through a real closure challenge you solved, naming the specific violation type, the constraints you adjusted, and the outcome at signoff.
Negotiate with competing offer timelines in mind
Semiconductor hiring cycles are long, so if you have an exploding offer, tell the competing team immediately and ask for a decision timeline. Teams that want you will compress their loop rather than lose a candidate who is already through their screen.
ASIC Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most asic engineers?
The most active employers for asic engineers right now are Meta, Apple, and Cisco, and the most openings are in California, Texas, and Colorado, based on current listings on Migrate Mate as of November 2026. Demand is especially concentrated at companies designing custom silicon for data center, mobile, and automotive applications.
How many asic engineer jobs are remote?
About 54% of asic engineer openings are fully remote or hybrid as of November 2026, which is lower than many engineering disciplines. Roles focused on RTL design and verification tend to offer the most remote flexibility, while physical design and post-silicon validation positions more often require on-site access to lab equipment and EDA license servers.
How do you become a asic engineer?
Start with a bachelor's degree in electrical or computer engineering with coursework in digital design, VLSI, and computer architecture. Build RTL design skills in Verilog or SystemVerilog through academic projects or open-source tape-outs. Gain exposure to EDA tools through university licenses or free versions, and pursue an internship or entry-level role on a design team to work through at least one full chip flow before targeting senior positions.
How do you get hired as an asic engineer with little experience?
Focus on completing a full RTL-to-GDSII flow on an open-source project, even at a simple node, so you can discuss every stage in an interview. Contribute to public chip design efforts on platforms like Google's OpenMPW program to gain tapeout credit. Entry-level roles at fabless startups and semiconductor IP companies are more likely to hire new graduates than large established chipmakers.
What does the asic engineer interview process look like?
Most processes start with a recruiter screen, followed by a technical phone interview covering digital design fundamentals, timing concepts, and coding in Verilog or SystemVerilog. A take-home design exercise or live coding session often follows. Final rounds typically include a system design discussion, a deep dive into past tapeout experience, and conversations with cross-functional partners in verification or physical design.
Where can I find and apply to asic engineer jobs?
You can find and apply to asic engineer jobs on Migrate Mate, which lists current openings from companies across the United States. Search for roles that match your specialization and experience level, then apply directly to each listing that fits.
See All 326+ ASIC Engineer Jobs
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Find ASIC Engineer Jobs