Electrical Engineer Jobs at Astera Labs with Visa Sponsorship
Astera Labs hires Electrical Engineers across hardware design, signal integrity, and high-speed interconnect disciplines, with a consistent track record of sponsoring international talent through both temporary work visas and permanent residence pathways for engineering roles.
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Get Access To All JobsINTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ROLE AND RESPONSIBILITIES
As an Astera Labs Physical Design/CAD Engineer, you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.
- As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
- Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
- Architect and recommend flow improvements and enhance existing methodology for high performance design.
- Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
- Work with cross function teams to define requirements and specifications to achieve best PPA.
- Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity.
- Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.
BASIC QUALIFICATIONS
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
- 2-8 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Strong scripting ability (Tcl, Python, Perl).
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
PREFERRED EXPERIENCE
- Knowledge of agentic AI solutions is a plus.
- Experience working with EDA/IP vendors for both RTL and hard-macro integration.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
LOCATION
Location: San Jose, California, United States
INTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ROLE AND RESPONSIBILITIES
As an Astera Labs Physical Design/CAD Engineer, you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.
- As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
- Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
- Architect and recommend flow improvements and enhance existing methodology for high performance design.
- Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
- Work with cross function teams to define requirements and specifications to achieve best PPA.
- Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity.
- Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.
BASIC QUALIFICATIONS
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
- 2-8 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Strong scripting ability (Tcl, Python, Perl).
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
PREFERRED EXPERIENCE
- Knowledge of agentic AI solutions is a plus.
- Experience working with EDA/IP vendors for both RTL and hard-macro integration.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
LOCATION
Location: San Jose, California, United States
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Get Access To All JobsTips for Finding Electrical Engineer Jobs at Astera Labs Jobs
Align your portfolio to interconnect hardware
Astera Labs focuses on semiconductor connectivity solutions, so frame your resume around PCB design, signal integrity, or high-speed SerDes experience. Hiring managers at companies like this look past general EE backgrounds toward candidates with domain-specific hardware depth.
Target roles that align with your visa category
H-1B sponsorship requires your role to qualify as a specialty occupation requiring a related bachelor's degree or higher. Electrical Engineer positions at Astera Labs routinely meet this standard, but hardware-adjacent roles with broader scope may face more scrutiny at USCIS.
Prepare for a multi-round technical interview process
Astera Labs' hardware engineering interviews typically involve schematic review, signal integrity problem-solving, and lab debugging scenarios. Having documented project work, simulation outputs, or tape-out experience ready to discuss directly strengthens your candidacy before an offer and sponsorship conversation begins.
Use Migrate Mate to surface open Electrical Engineer roles
Astera Labs posts Electrical Engineer positions across multiple job boards, but not all listings disclose sponsorship availability. Use Migrate Mate to filter specifically for Astera Labs roles that include visa sponsorship so you're not wasting applications on postings that won't support your status.
Clarify Green Card intent during the offer stage
If long-term sponsorship matters to you, raise EB-2 or EB-3 PERM sponsorship expectations before signing an offer. Hardware-focused employers in this sector routinely support Green Card filings for engineers who demonstrate retention value, so it's a practical conversation to have early.
Electrical Engineer at Astera Labs jobs are hiring across the US. Find yours.
Find Electrical Engineer at Astera Labs JobsFrequently Asked Questions
Does Astera Labs sponsor H-1B visas for Electrical Engineers?
Yes, Astera Labs sponsors H-1B visas for Electrical Engineer roles. The company has a consistent record of supporting work visa filings for engineering talent, and Electrical Engineer positions typically qualify as specialty occupations under USCIS criteria given the degree requirements involved. If you're cap-subject, timing your application to the April H-1B lottery window is essential.
How do I apply for Electrical Engineer jobs at Astera Labs?
Applications go through Astera Labs' careers page, where you can filter by engineering discipline. To find roles that explicitly include visa sponsorship, Migrate Mate lets you browse Astera Labs' open Electrical Engineer positions filtered by sponsorship availability, saving you from applying to postings that won't support your immigration status. Tailor your resume to hardware design and connectivity systems to match the company's core work.
Which visa types does Astera Labs use for Electrical Engineers?
Astera Labs sponsors Electrical Engineers through H-1B for specialty occupation roles, F-1 OPT and OPT STEM extension for recent graduates, TN visas for Canadian and Mexican nationals in qualifying engineering categories, and EB-2 or EB-3 immigrant visa pathways for permanent residence. The right visa depends on your nationality, degree level, and where you are in your career stage.
What qualifications does Astera Labs expect for Electrical Engineer roles?
Most Electrical Engineer roles at Astera Labs require a bachelor's degree in Electrical Engineering or a closely related field, with stronger candidates holding master's degrees or relevant hardware experience. Practical depth in areas like signal integrity, high-speed digital design, PCB layout, or semiconductor-level systems is typically more important than breadth across general EE disciplines when targeting this company specifically.
How long does the sponsorship and hiring process take at Astera Labs?
From interview to offer typically takes four to eight weeks at a hardware-focused semiconductor company. If you need H-1B sponsorship and are cap-subject, USCIS processing adds several months, with employment starting October 1 at the earliest following an April lottery selection. STEM OPT and TN sponsorship move faster since neither is lottery-dependent, making them common bridges while H-1B petitions are pending.
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