Engineering Jobs at Astera Labs with Visa Sponsorship
Engineering jobs at Astera Labs span silicon design, firmware, and systems integration, as the company builds semiconductor and connectivity solutions at the edge of what modern data infrastructure demands. The company has an active sponsorship track record for Engineering candidates across H-1B visa, OPT, and permanent residence pathways.
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Get Access To All JobsINTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ABOUT THE ROLE
We are seeking an experienced Director of Design for Test (DFT) to lead our DFT engineering efforts for the Scorpio family of PCIe switch products. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale. This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.
KEY RESPONSIBILITIES
DFT Strategy & Leadership
- Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging
- Lead and mentor a team of DFT engineers across multiple product development cycles
- Collaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing cost
- Establish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurations
Advanced Packaging DFT Architecture
- Develop DFT strategies for 2.5D/3D heterogeneous integration architectures:
- Multi-die test access and coordination through silicon interposers
- Through-Silicon Via (TSV) testing and characterization
- Die-to-die interface testing and Known Good Die (KGD) strategies
- Chiplet-level DFT with system-level test integration
- Hybrid bonding and micro-bump interconnect testing
- Architect test access mechanisms for:
- Inter-die communication channels and high-bandwidth interfaces
- HBM/DRAM interfaces in 2.5D configurations
- Power delivery network testing across multiple dies
- Thermal and reliability test structures
- Define pre-bond and post-bond test strategies:
- Individual die screening and KGD qualification
- Stack-level testing for 3D integrated circuits
- Package-level test optimization and cost reduction
Technical Execution
- Architect and implement advanced DFT features including:
- Scan insertion, ATPG, and compression strategies for multi-die systems
- Memory BIST (MBIST) for embedded SRAM and register files
- Logic BIST (LBIST) for at-speed testing
- IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) for die-level and package-level access
- IEEE 1838 (3D-DFT) standards for 3D stacked die test
- High-speed SerDes BIST and loopback testing across die boundaries
- Analog/mixed-signal test hooks and observability
- Built-in Self-Repair (BISR) for redundancy management
- Drive fault coverage targets (>99% stuck-at, >95% transition) across all dies
- Optimize test time and ATE costs while maintaining quality metrics
- Define and implement production test programs and diagnostic capabilities for packaged devices
Cross-Functional Collaboration
- Partner with physical design and packaging teams to optimize DFT area, timing, and package routing impact
- Work with silicon validation teams to enable post-silicon debug and characterization of multi-die systems
- Collaborate with manufacturing, assembly, and test engineering for seamless production ramp
- Interface with OSAT partners, substrate vendors, and ATE vendors
- Coordinate with design teams on die partitioning and test accessibility planning
Quality & Reliability
- Define test coverage metrics and quality goals for multi-die products
- Implement diagnostic and failure analysis capabilities for complex packaging failures
- Support yield enhancement and defect reduction initiatives across die and package
- Establish field return analysis and root cause investigation processes
- Develop screening strategies for infant mortality and reliability issues
REQUIRED QUALIFICATIONS
Education & Experience
- MS or PhD in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in DFT engineering with complex SoC/ASIC products
- 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies
- 5+ years in technical leadership or management roles
- Proven track record of multiple successful tape-outs with high-volume production
- Experience taking multi-die products from design through production ramp
Technical Expertise
- Deep expertise in DFT methodologies and industry standards
- Strong background in 2.5D/3D packaging technologies:
- Silicon interposer-based designs
- TSV technology and testing
- Chiplet architectures and die-to-die interfaces
- Known Good Die (KGD) test strategies
- CoWoS, EMIB, or similar advanced packaging platforms
- Understanding of JEDEC standards for multi-die testing (e.g., JESD229, JESD235)
- Experience with DFT EDA tools (Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, etc.)
- Strong understanding of ASIC design flow from RTL to GDS
- Knowledge of high-speed SerDes architectures and testing requirements
- Familiarity with ATE platforms (Advantest, Teradyne) and test program development for advanced packages
- Understanding of production test economics and yield analysis for multi-die products
- Experience with IEEE 1149.1, IEEE 1687 (IJTAG), and IEEE 1838 (3D-DFT) standards
Leadership & Communication
- Proven ability to build, lead, and mentor high-performing engineering teams
- Excellent communication skills with ability to influence across organizations
- Strategic thinking with strong execution and problem-solving capabilities
- Experience managing projects with competing priorities and tight schedules
- Ability to work effectively with external partners (OSATs, packaging vendors)
PREFERRED QUALIFICATIONS
- Experience with PCIe, CXL, or other high-speed serial protocols
- Background in SerDes architecture and testing
- Experience with HBM (High Bandwidth Memory) testing in 2.5D packages
- Knowledge of chiplet-based system architectures (UCIe, BoW, AIB)
- Familiarity with 3D stacking technologies (face-to-face, face-to-back bonding)
- Experience with wafer-level testing and probe strategies for advanced packages
- Familiarity with functional safety requirements (ISO 26262) or automotive quality standards
- Experience with machine learning approaches to test optimization
- Understanding of PCIe/CXL link training, equalization, and state machines
- Prior experience in networking or switch product development
- Knowledge of thermal and power integrity considerations in 3D packages
- Experience with DTCO (Design-Technology Co-Optimization) for advanced nodes and packaging
This position can be hired as a Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
INTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ABOUT THE ROLE
We are seeking an experienced Director of Design for Test (DFT) to lead our DFT engineering efforts for the Scorpio family of PCIe switch products. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale. This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.
KEY RESPONSIBILITIES
DFT Strategy & Leadership
- Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging
- Lead and mentor a team of DFT engineers across multiple product development cycles
- Collaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing cost
- Establish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurations
Advanced Packaging DFT Architecture
- Develop DFT strategies for 2.5D/3D heterogeneous integration architectures:
- Multi-die test access and coordination through silicon interposers
- Through-Silicon Via (TSV) testing and characterization
- Die-to-die interface testing and Known Good Die (KGD) strategies
- Chiplet-level DFT with system-level test integration
- Hybrid bonding and micro-bump interconnect testing
- Architect test access mechanisms for:
- Inter-die communication channels and high-bandwidth interfaces
- HBM/DRAM interfaces in 2.5D configurations
- Power delivery network testing across multiple dies
- Thermal and reliability test structures
- Define pre-bond and post-bond test strategies:
- Individual die screening and KGD qualification
- Stack-level testing for 3D integrated circuits
- Package-level test optimization and cost reduction
Technical Execution
- Architect and implement advanced DFT features including:
- Scan insertion, ATPG, and compression strategies for multi-die systems
- Memory BIST (MBIST) for embedded SRAM and register files
- Logic BIST (LBIST) for at-speed testing
- IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) for die-level and package-level access
- IEEE 1838 (3D-DFT) standards for 3D stacked die test
- High-speed SerDes BIST and loopback testing across die boundaries
- Analog/mixed-signal test hooks and observability
- Built-in Self-Repair (BISR) for redundancy management
- Drive fault coverage targets (>99% stuck-at, >95% transition) across all dies
- Optimize test time and ATE costs while maintaining quality metrics
- Define and implement production test programs and diagnostic capabilities for packaged devices
Cross-Functional Collaboration
- Partner with physical design and packaging teams to optimize DFT area, timing, and package routing impact
- Work with silicon validation teams to enable post-silicon debug and characterization of multi-die systems
- Collaborate with manufacturing, assembly, and test engineering for seamless production ramp
- Interface with OSAT partners, substrate vendors, and ATE vendors
- Coordinate with design teams on die partitioning and test accessibility planning
Quality & Reliability
- Define test coverage metrics and quality goals for multi-die products
- Implement diagnostic and failure analysis capabilities for complex packaging failures
- Support yield enhancement and defect reduction initiatives across die and package
- Establish field return analysis and root cause investigation processes
- Develop screening strategies for infant mortality and reliability issues
REQUIRED QUALIFICATIONS
Education & Experience
- MS or PhD in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in DFT engineering with complex SoC/ASIC products
- 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies
- 5+ years in technical leadership or management roles
- Proven track record of multiple successful tape-outs with high-volume production
- Experience taking multi-die products from design through production ramp
Technical Expertise
- Deep expertise in DFT methodologies and industry standards
- Strong background in 2.5D/3D packaging technologies:
- Silicon interposer-based designs
- TSV technology and testing
- Chiplet architectures and die-to-die interfaces
- Known Good Die (KGD) test strategies
- CoWoS, EMIB, or similar advanced packaging platforms
- Understanding of JEDEC standards for multi-die testing (e.g., JESD229, JESD235)
- Experience with DFT EDA tools (Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, etc.)
- Strong understanding of ASIC design flow from RTL to GDS
- Knowledge of high-speed SerDes architectures and testing requirements
- Familiarity with ATE platforms (Advantest, Teradyne) and test program development for advanced packages
- Understanding of production test economics and yield analysis for multi-die products
- Experience with IEEE 1149.1, IEEE 1687 (IJTAG), and IEEE 1838 (3D-DFT) standards
Leadership & Communication
- Proven ability to build, lead, and mentor high-performing engineering teams
- Excellent communication skills with ability to influence across organizations
- Strategic thinking with strong execution and problem-solving capabilities
- Experience managing projects with competing priorities and tight schedules
- Ability to work effectively with external partners (OSATs, packaging vendors)
PREFERRED QUALIFICATIONS
- Experience with PCIe, CXL, or other high-speed serial protocols
- Background in SerDes architecture and testing
- Experience with HBM (High Bandwidth Memory) testing in 2.5D packages
- Knowledge of chiplet-based system architectures (UCIe, BoW, AIB)
- Familiarity with 3D stacking technologies (face-to-face, face-to-back bonding)
- Experience with wafer-level testing and probe strategies for advanced packages
- Familiarity with functional safety requirements (ISO 26262) or automotive quality standards
- Experience with machine learning approaches to test optimization
- Understanding of PCIe/CXL link training, equalization, and state machines
- Prior experience in networking or switch product development
- Knowledge of thermal and power integrity considerations in 3D packages
- Experience with DTCO (Design-Technology Co-Optimization) for advanced nodes and packaging
This position can be hired as a Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Tips for Finding Engineering Jobs at Astera Labs
Align your credentials to specialty occupation standards
H-1B eligibility requires your degree field to match the Engineering role directly. For semiconductor and hardware positions at Astera Labs, a degree in electrical engineering, computer engineering, or a closely related discipline strengthens your specialty occupation case considerably.
Target roles matching your OPT STEM extension window
F-1 students with a STEM OPT extension have up to three years of work authorization. Astera Labs hires across firmware, silicon validation, and systems roles, so prioritize applications where your degree field aligns to maximize your window before the next H-1B cap season.
Research Astera Labs filings through DOL disclosure data
DOL Labor Condition Application records show which Engineering job titles Astera Labs has filed for historically. Filtering by employer name surfaces the role classifications and prevailing wage levels the company has used, helping you frame your application around their established hiring patterns.
Flag sponsorship willingness early in conversations
Astera Labs operates in a specialized semiconductor segment where qualified Engineers are scarce. Raising visa sponsorship in early recruiter conversations is reasonable here, because hiring teams in Electronics and Hardware are accustomed to international candidates and can confirm their process upfront.
Understand the LCA timeline before accepting an offer
Your employer files a Labor Condition Application with DOL before submitting your H-1B petition to USCIS. LCA certification typically takes seven business days, so factor this into your start date negotiation to avoid gaps between authorization and your first day.
Use Migrate Mate to find open Engineering roles
Sponsorship-eligible Engineering positions at Astera Labs aren't always labeled clearly on general job boards. Use Migrate Mate to browse and filter verified visa-sponsoring roles at Astera Labs so you're applying to positions where sponsorship is already confirmed.
Frequently Asked Questions
Does Astera Labs sponsor H-1B visas for Engineers?
Yes, Astera Labs sponsors H-1B visas for Engineering roles. The company has a consistent track record of filing H-1B petitions for technical positions across its semiconductor and connectivity product lines, including hardware design, firmware, and systems engineering. If you're in a relevant Engineering discipline, H-1B sponsorship is a realistic path with this employer.
Which visa types does Astera Labs commonly use for Engineering roles?
Astera Labs sponsors Engineering candidates on H-1B, F-1 OPT (including the STEM extension), TN visa for Canadian and Mexican nationals in qualifying Engineering classifications, and permanent residence through EB-2 and EB-3 categories. The right pathway depends on your nationality, degree field, and where you are in your career. For senior or specialized Engineering roles, EB-2 is the more common green card route.
What qualifications does Astera Labs expect for Engineering roles?
Most Engineering roles at Astera Labs require a bachelor's degree or higher in electrical engineering, computer engineering, or a related field. For H-1B purposes, your degree must directly correspond to the position's duties. Roles in silicon validation, PCIe and CXL protocol development, and systems integration are common at Astera Labs, and relevant industry experience in high-speed interconnects or data center hardware strengthens your profile.
How do I apply for Engineering jobs at Astera Labs?
Browse open Engineering positions at Astera Labs through Migrate Mate, which surfaces roles where visa sponsorship is confirmed. Once you identify a match, apply directly through Astera Labs' careers portal. Tailor your resume to highlight hardware or firmware experience relevant to their product lines, and be prepared to discuss your visa status and timeline during the initial recruiter screen.
How do I time my application around the H-1B cap season?
USCIS opens H-1B registrations in March each year for an October 1 start date. If you're on F-1 OPT, you need work authorization that bridges from your OPT expiration to October 1. Start your Astera Labs application at least six months before your OPT end date so there's enough runway for the offer, LCA filing, and H-1B petition if you're selected in the lottery.