Design Engineer Jobs at Astera Labs with Visa Sponsorship
Design Engineer jobs at Astera Labs sit at the intersection of high-speed connectivity and semiconductor innovation, covering analog, digital, and mixed-signal work across their PCIe and CXL product lines. Astera Labs has a consistent record of sponsoring work visas for engineering talent in this function.
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Get Access To All JobsINTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
Join Astera Labs as a Senior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up. You'll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world's most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale.
Key Responsibilities
- RTL Design & Implementation
- Own the RTL implementation of complex digital designs from micro-architecture through sign-off
- Design and implement CPU subsystems and embedded processor interfaces
- Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments
- Verification & Quality
- Collaborate with verification teams to review test plans and debug issues
- Support efforts to achieve timing closure and implement Design-for-Test (DFT) features
-
Accountable for quality and overall design success with the support of senior engineers
-
Methodology & Automation
- Scripting and automation for ASIC methodology improvement
- Contribute to design infrastructure that improves team productivity and design quality
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering or equivalent
- 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
- Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence
- Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)
- Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations)
- Experience with clocking, CDC, and RDC methodologies
- Proficiency in SystemVerilog and Python in a production environment
PREFERRED QUALIFICATIONS
- Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)
- Familiarity with high-speed protocols—PCIe Gen 6/7, Ethernet, UALink, or UCI
- Experience with CMOS nodes (≤7nm)
- Exposure to embedded firmware development or secure firmware boot flows
- Experience with functional and formal verification at block and chip level
- Familiarity with UVM-based verification methodologies
Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
INTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
Join Astera Labs as a Senior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up. You'll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world's most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale.
Key Responsibilities
- RTL Design & Implementation
- Own the RTL implementation of complex digital designs from micro-architecture through sign-off
- Design and implement CPU subsystems and embedded processor interfaces
- Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments
- Verification & Quality
- Collaborate with verification teams to review test plans and debug issues
- Support efforts to achieve timing closure and implement Design-for-Test (DFT) features
-
Accountable for quality and overall design success with the support of senior engineers
-
Methodology & Automation
- Scripting and automation for ASIC methodology improvement
- Contribute to design infrastructure that improves team productivity and design quality
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering or equivalent
- 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
- Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence
- Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)
- Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations)
- Experience with clocking, CDC, and RDC methodologies
- Proficiency in SystemVerilog and Python in a production environment
PREFERRED QUALIFICATIONS
- Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)
- Familiarity with high-speed protocols—PCIe Gen 6/7, Ethernet, UALink, or UCI
- Experience with CMOS nodes (≤7nm)
- Exposure to embedded firmware development or secure firmware boot flows
- Experience with functional and formal verification at block and chip level
- Familiarity with UVM-based verification methodologies
Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
See all Design Engineer Jobs at Astera Labs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Engineer Jobs at Astera Labs.
Get Access To All JobsTips for Finding Design Engineer Jobs at Astera Labs
Align your portfolio to PCIe and CXL
Astera Labs builds connectivity silicon for data center infrastructure. Before applying, reframe your design experience around high-speed serial interfaces, signal integrity, or memory bus protocols so your background maps directly to their active product areas.
Verify your credentials match specialty occupation standards
H-1B approval for Design Engineer roles requires USCIS to confirm the position demands a specific bachelor's degree field. Make sure your degree in electrical engineering, computer engineering, or a directly related discipline is clearly documented before your employer files.
Search Design Engineer openings through Migrate Mate
Filter Migrate Mate's job board by company and role to surface active Design Engineer postings at Astera Labs that explicitly list visa sponsorship, so you're not guessing which listings are open to sponsored candidates.
Target Astera Labs during H-1B registration windows
H-1B registration opens in March each year for an October 1 start date. If you're on F-1 OPT, time your Astera Labs application so an offer can be in place before the registration deadline, giving your employer enough runway to file.
Prepare for a technical screen centered on analog and mixed-signal design
Astera Labs' Design Engineer interviews typically probe transistor-level circuit design, noise analysis, and layout constraints. A strong performance here directly influences whether the hiring team moves quickly to an offer and initiates sponsorship paperwork.
Confirm your employer's PERM readiness for permanent residency
If you're targeting a Green Card through EB-2 or EB-3, ask your recruiter early whether Astera Labs has an established PERM process. DOL requires a documented recruitment effort, so earlier internal alignment means fewer delays when you're ready to file.
Frequently Asked Questions
Does Astera Labs sponsor H-1B visas for Design Engineers?
Yes, Astera Labs sponsors H-1B visas for Design Engineer roles. The company has a consistent pattern of filing H-1B petitions for engineering positions, including hardware and silicon design functions. If you're on F-1 OPT or another nonimmigrant status, it's worth confirming sponsorship intent during the recruiter screen before progressing through the full interview process.
Which visa types does Astera Labs commonly use for Design Engineer roles?
Astera Labs sponsors H-1B visas as the primary work authorization pathway for Design Engineers, along with F-1 OPT extensions for recent graduates and TN visas for Canadian and Mexican nationals in qualifying engineering roles. For longer-term pathways, the company also supports EB-2 and EB-3 Green Card sponsorship, which involves PERM labor certification filed through the Department of Labor.
What qualifications does Astera Labs expect for Design Engineer roles?
Astera Labs typically expects a bachelor's or master's degree in electrical engineering, computer engineering, or a closely related field. For hardware-focused Design Engineer positions, experience with high-speed digital or analog circuit design, signal integrity, or VLSI methodologies is commonly required. Familiarity with PCIe, CXL, or similar serial interconnect standards is particularly relevant given their product focus.
How do I apply for Design Engineer jobs at Astera Labs?
You can browse and apply for Design Engineer roles at Astera Labs through Migrate Mate, which surfaces sponsorship-friendly postings from the company in one place. Once you identify a role, apply directly through the company's careers page and flag your visa status early in the process. Astera Labs' recruiting team typically moves candidates through a technical phone screen followed by a structured onsite or virtual loop.
How do I time my application to Astera Labs around the H-1B cap?
H-1B registration runs each March for an October 1 start date. If you're on F-1 OPT, you need an offer letter in place before the USCIS registration window opens so your employer can submit your registration. Engage Astera Labs' recruiting team no later than January or February if you're targeting the current cap cycle, and confirm they're prepared to file during that window.