Design Engineer Jobs at Astera Labs with Visa Sponsorship
Design Engineer jobs at Astera Labs sit at the intersection of high-speed connectivity and semiconductor innovation, covering analog, digital, and mixed-signal work across their PCIe and CXL product lines. Astera Labs has a consistent record of sponsoring work visas for engineering talent in this function.
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Get Access To All JobsINTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ABOUT THE ROLE
We are seeking an experienced Director of Design for Test (DFT) to lead our DFT engineering efforts for the Scorpio family of PCIe switch products. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale. This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.
KEY RESPONSIBILITIES
DFT Strategy & Leadership
- Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging
- Lead and mentor a team of DFT engineers across multiple product development cycles
- Collaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing cost
- Establish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurations
Advanced Packaging DFT Architecture
- Develop DFT strategies for 2.5D/3D heterogeneous integration architectures:
- Multi-die test access and coordination through silicon interposers
- Through-Silicon Via (TSV) testing and characterization
- Die-to-die interface testing and Known Good Die (KGD) strategies
- Chiplet-level DFT with system-level test integration
- Hybrid bonding and micro-bump interconnect testing
- Architect test access mechanisms for:
- Inter-die communication channels and high-bandwidth interfaces
- HBM/DRAM interfaces in 2.5D configurations
- Power delivery network testing across multiple dies
- Thermal and reliability test structures
- Define pre-bond and post-bond test strategies:
- Individual die screening and KGD qualification
- Stack-level testing for 3D integrated circuits
- Package-level test optimization and cost reduction
Technical Execution
- Architect and implement advanced DFT features including:
- Scan insertion, ATPG, and compression strategies for multi-die systems
- Memory BIST (MBIST) for embedded SRAM and register files
- Logic BIST (LBIST) for at-speed testing
- IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) for die-level and package-level access
- IEEE 1838 (3D-DFT) standards for 3D stacked die test
- High-speed SerDes BIST and loopback testing across die boundaries
- Analog/mixed-signal test hooks and observability
- Built-in Self-Repair (BISR) for redundancy management
- Drive fault coverage targets (>99% stuck-at, >95% transition) across all dies
- Optimize test time and ATE costs while maintaining quality metrics
- Define and implement production test programs and diagnostic capabilities for packaged devices
Cross-Functional Collaboration
- Partner with physical design and packaging teams to optimize DFT area, timing, and package routing impact
- Work with silicon validation teams to enable post-silicon debug and characterization of multi-die systems
- Collaborate with manufacturing, assembly, and test engineering for seamless production ramp
- Interface with OSAT partners, substrate vendors, and ATE vendors
- Coordinate with design teams on die partitioning and test accessibility planning
Quality & Reliability
- Define test coverage metrics and quality goals for multi-die products
- Implement diagnostic and failure analysis capabilities for complex packaging failures
- Support yield enhancement and defect reduction initiatives across die and package
- Establish field return analysis and root cause investigation processes
- Develop screening strategies for infant mortality and reliability issues
REQUIRED QUALIFICATIONS
Education & Experience
- MS or PhD in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in DFT engineering with complex SoC/ASIC products
- 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies
- 5+ years in technical leadership or management roles
- Proven track record of multiple successful tape-outs with high-volume production
- Experience taking multi-die products from design through production ramp
Technical Expertise
- Deep expertise in DFT methodologies and industry standards
- Strong background in 2.5D/3D packaging technologies:
- Silicon interposer-based designs
- TSV technology and testing
- Chiplet architectures and die-to-die interfaces
- Known Good Die (KGD) test strategies
- CoWoS, EMIB, or similar advanced packaging platforms
- Understanding of JEDEC standards for multi-die testing (e.g., JESD229, JESD235)
- Experience with DFT EDA tools (Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, etc.)
- Strong understanding of ASIC design flow from RTL to GDS
- Knowledge of high-speed SerDes architectures and testing requirements
- Familiarity with ATE platforms (Advantest, Teradyne) and test program development for advanced packages
- Understanding of production test economics and yield analysis for multi-die products
- Experience with IEEE 1149.1, IEEE 1687 (IJTAG), and IEEE 1838 (3D-DFT) standards
Leadership & Communication
- Proven ability to build, lead, and mentor high-performing engineering teams
- Excellent communication skills with ability to influence across organizations
- Strategic thinking with strong execution and problem-solving capabilities
- Experience managing projects with competing priorities and tight schedules
- Ability to work effectively with external partners (OSATs, packaging vendors)
PREFERRED QUALIFICATIONS
- Experience with PCIe, CXL, or other high-speed serial protocols
- Background in SerDes architecture and testing
- Experience with HBM (High Bandwidth Memory) testing in 2.5D packages
- Knowledge of chiplet-based system architectures (UCIe, BoW, AIB)
- Familiarity with 3D stacking technologies (face-to-face, face-to-back bonding)
- Experience with wafer-level testing and probe strategies for advanced packages
- Familiarity with functional safety requirements (ISO 26262) or automotive quality standards
- Experience with machine learning approaches to test optimization
- Understanding of PCIe/CXL link training, equalization, and state machines
- Prior experience in networking or switch product development
- Knowledge of thermal and power integrity considerations in 3D packages
- Experience with DTCO (Design-Technology Co-Optimization) for advanced nodes and packaging
This position can be hired as a Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
INTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ABOUT THE ROLE
We are seeking an experienced Director of Design for Test (DFT) to lead our DFT engineering efforts for the Scorpio family of PCIe switch products. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale. This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.
KEY RESPONSIBILITIES
DFT Strategy & Leadership
- Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging
- Lead and mentor a team of DFT engineers across multiple product development cycles
- Collaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing cost
- Establish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurations
Advanced Packaging DFT Architecture
- Develop DFT strategies for 2.5D/3D heterogeneous integration architectures:
- Multi-die test access and coordination through silicon interposers
- Through-Silicon Via (TSV) testing and characterization
- Die-to-die interface testing and Known Good Die (KGD) strategies
- Chiplet-level DFT with system-level test integration
- Hybrid bonding and micro-bump interconnect testing
- Architect test access mechanisms for:
- Inter-die communication channels and high-bandwidth interfaces
- HBM/DRAM interfaces in 2.5D configurations
- Power delivery network testing across multiple dies
- Thermal and reliability test structures
- Define pre-bond and post-bond test strategies:
- Individual die screening and KGD qualification
- Stack-level testing for 3D integrated circuits
- Package-level test optimization and cost reduction
Technical Execution
- Architect and implement advanced DFT features including:
- Scan insertion, ATPG, and compression strategies for multi-die systems
- Memory BIST (MBIST) for embedded SRAM and register files
- Logic BIST (LBIST) for at-speed testing
- IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) for die-level and package-level access
- IEEE 1838 (3D-DFT) standards for 3D stacked die test
- High-speed SerDes BIST and loopback testing across die boundaries
- Analog/mixed-signal test hooks and observability
- Built-in Self-Repair (BISR) for redundancy management
- Drive fault coverage targets (>99% stuck-at, >95% transition) across all dies
- Optimize test time and ATE costs while maintaining quality metrics
- Define and implement production test programs and diagnostic capabilities for packaged devices
Cross-Functional Collaboration
- Partner with physical design and packaging teams to optimize DFT area, timing, and package routing impact
- Work with silicon validation teams to enable post-silicon debug and characterization of multi-die systems
- Collaborate with manufacturing, assembly, and test engineering for seamless production ramp
- Interface with OSAT partners, substrate vendors, and ATE vendors
- Coordinate with design teams on die partitioning and test accessibility planning
Quality & Reliability
- Define test coverage metrics and quality goals for multi-die products
- Implement diagnostic and failure analysis capabilities for complex packaging failures
- Support yield enhancement and defect reduction initiatives across die and package
- Establish field return analysis and root cause investigation processes
- Develop screening strategies for infant mortality and reliability issues
REQUIRED QUALIFICATIONS
Education & Experience
- MS or PhD in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in DFT engineering with complex SoC/ASIC products
- 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies
- 5+ years in technical leadership or management roles
- Proven track record of multiple successful tape-outs with high-volume production
- Experience taking multi-die products from design through production ramp
Technical Expertise
- Deep expertise in DFT methodologies and industry standards
- Strong background in 2.5D/3D packaging technologies:
- Silicon interposer-based designs
- TSV technology and testing
- Chiplet architectures and die-to-die interfaces
- Known Good Die (KGD) test strategies
- CoWoS, EMIB, or similar advanced packaging platforms
- Understanding of JEDEC standards for multi-die testing (e.g., JESD229, JESD235)
- Experience with DFT EDA tools (Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, etc.)
- Strong understanding of ASIC design flow from RTL to GDS
- Knowledge of high-speed SerDes architectures and testing requirements
- Familiarity with ATE platforms (Advantest, Teradyne) and test program development for advanced packages
- Understanding of production test economics and yield analysis for multi-die products
- Experience with IEEE 1149.1, IEEE 1687 (IJTAG), and IEEE 1838 (3D-DFT) standards
Leadership & Communication
- Proven ability to build, lead, and mentor high-performing engineering teams
- Excellent communication skills with ability to influence across organizations
- Strategic thinking with strong execution and problem-solving capabilities
- Experience managing projects with competing priorities and tight schedules
- Ability to work effectively with external partners (OSATs, packaging vendors)
PREFERRED QUALIFICATIONS
- Experience with PCIe, CXL, or other high-speed serial protocols
- Background in SerDes architecture and testing
- Experience with HBM (High Bandwidth Memory) testing in 2.5D packages
- Knowledge of chiplet-based system architectures (UCIe, BoW, AIB)
- Familiarity with 3D stacking technologies (face-to-face, face-to-back bonding)
- Experience with wafer-level testing and probe strategies for advanced packages
- Familiarity with functional safety requirements (ISO 26262) or automotive quality standards
- Experience with machine learning approaches to test optimization
- Understanding of PCIe/CXL link training, equalization, and state machines
- Prior experience in networking or switch product development
- Knowledge of thermal and power integrity considerations in 3D packages
- Experience with DTCO (Design-Technology Co-Optimization) for advanced nodes and packaging
This position can be hired as a Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
See all Design Engineer Jobs at Astera Labs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Engineer Jobs at Astera Labs.
Get Access To All JobsTips for Finding Design Engineer Jobs at Astera Labs
Align your portfolio to PCIe and CXL
Astera Labs builds connectivity silicon for data center infrastructure. Before applying, reframe your design experience around high-speed serial interfaces, signal integrity, or memory bus protocols so your background maps directly to their active product areas.
Verify your credentials match specialty occupation standards
H-1B approval for Design Engineer roles requires USCIS to confirm the position demands a specific bachelor's degree field. Make sure your degree in electrical engineering, computer engineering, or a directly related discipline is clearly documented before your employer files.
Search Design Engineer openings through Migrate Mate
Filter Migrate Mate's job board by company and role to surface active Design Engineer postings at Astera Labs that explicitly list visa sponsorship, so you're not guessing which listings are open to sponsored candidates.
Target Astera Labs during H-1B registration windows
H-1B registration opens in March each year for an October 1 start date. If you're on F-1 OPT, time your Astera Labs application so an offer can be in place before the registration deadline, giving your employer enough runway to file.
Prepare for a technical screen centered on analog and mixed-signal design
Astera Labs' Design Engineer interviews typically probe transistor-level circuit design, noise analysis, and layout constraints. A strong performance here directly influences whether the hiring team moves quickly to an offer and initiates sponsorship paperwork.
Confirm your employer's PERM readiness for permanent residency
If you're targeting a Green Card through EB-2 or EB-3, ask your recruiter early whether Astera Labs has an established PERM process. DOL requires a documented recruitment effort, so earlier internal alignment means fewer delays when you're ready to file.
Frequently Asked Questions
Does Astera Labs sponsor H-1B visas for Design Engineers?
Yes, Astera Labs sponsors H-1B visas for Design Engineer roles. The company has a consistent pattern of filing H-1B petitions for engineering positions, including hardware and silicon design functions. If you're on F-1 OPT or another nonimmigrant status, it's worth confirming sponsorship intent during the recruiter screen before progressing through the full interview process.
Which visa types does Astera Labs commonly use for Design Engineer roles?
Astera Labs sponsors H-1B visas as the primary work authorization pathway for Design Engineers, along with F-1 OPT extensions for recent graduates and TN visas for Canadian and Mexican nationals in qualifying engineering roles. For longer-term pathways, the company also supports EB-2 and EB-3 Green Card sponsorship, which involves PERM labor certification filed through the Department of Labor.
What qualifications does Astera Labs expect for Design Engineer roles?
Astera Labs typically expects a bachelor's or master's degree in electrical engineering, computer engineering, or a closely related field. For hardware-focused Design Engineer positions, experience with high-speed digital or analog circuit design, signal integrity, or VLSI methodologies is commonly required. Familiarity with PCIe, CXL, or similar serial interconnect standards is particularly relevant given their product focus.
How do I apply for Design Engineer jobs at Astera Labs?
You can browse and apply for Design Engineer roles at Astera Labs through Migrate Mate, which surfaces sponsorship-friendly postings from the company in one place. Once you identify a role, apply directly through the company's careers page and flag your visa status early in the process. Astera Labs' recruiting team typically moves candidates through a technical phone screen followed by a structured onsite or virtual loop.
How do I time my application to Astera Labs around the H-1B cap?
H-1B registration runs each March for an October 1 start date. If you're on F-1 OPT, you need an offer letter in place before the USCIS registration window opens so your employer can submit your registration. Engage Astera Labs' recruiting team no later than January or February if you're targeting the current cap cycle, and confirm they're prepared to file during that window.