Design Engineer Jobs at Micron Technology with Visa Sponsorship
Design Engineer jobs at Micron Technology span memory, storage, and semiconductor process development, with roles across front-end circuit design, physical implementation, and verification. The company has a consistent record of sponsoring work visas for this function, making it a realistic target for internationally qualified engineers.
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Get Access To All JobsINTRODUCTION
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
ROLE AND RESPONSIBILITIES
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
- Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
- Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
- Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
BASIC QUALIFICATIONS
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
PREFERRED QUALIFICATIONS
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
- Minimum 3 years of experience in a related field.
- Proven ability to mentor and develop engineers early in their careers.
- Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
COMPENSATION
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$103,000.00 - $210,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
BENEFITS
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
INTRODUCTION
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
ROLE AND RESPONSIBILITIES
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
- Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
- Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
- Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
BASIC QUALIFICATIONS
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
PREFERRED QUALIFICATIONS
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
- Minimum 3 years of experience in a related field.
- Proven ability to mentor and develop engineers early in their careers.
- Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
COMPENSATION
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$103,000.00 - $210,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
BENEFITS
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
See all 141+ Design Engineer Jobs at Micron Technology
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Engineer Jobs at Micron Technology.
Get Access To All JobsTips for Finding Design Engineer Jobs at Micron Technology
Align your portfolio to process nodes
Micron recruits Design Engineers to work on DRAM, NAND, and advanced packaging. Tailor your resume and project portfolio to reflect experience at relevant process nodes, whether that is sub-10nm logic design or high-density memory array architecture.
Target roles before the H-1B registration window
Micron files H-1B petitions on the April 1 start date. If you are on OPT, timing your offer to land before the March USCIS registration window gives your employer the clearest runway to file without gaps in your authorization.
Verify your degree maps to specialty occupation criteria
USCIS requires a direct connection between your degree field and the Design Engineer role. A degree in electrical engineering or computer engineering maps cleanly. If yours is in a related but adjacent field, prepare documentation showing coursework that directly covers circuit design or semiconductor systems.
Understand how Micron structures LCA filings
Micron lists its Labor Condition Applications through DOL, covering specific worksites including fabs and design centers in Boise, Milpitas, and Atlanta. Confirm the location on your offer letter matches the LCA worksite before your employer submits the H-1B petition.
Use Migrate Mate to find open Design Engineer roles
Micron posts Design Engineer openings across multiple sites and specializations at different times of year. Use Migrate Mate to filter for visa-sponsored Design Engineer roles at Micron specifically, so you are applying to positions where sponsorship is already confirmed rather than negotiating it later.
Plan for Green Card timelines if you are from India
Micron sponsors EB-2 and EB-3 Green Cards, but EB-3 India backlogs run decades out. If you are an Indian national, ask during the offer stage whether the role qualifies for EB-2 NIW or a PERM-based EB-2 filing, which carries a shorter wait in most cases.
Frequently Asked Questions
Does Micron Technology sponsor H-1B visas for Design Engineers?
Yes, Micron Technology sponsors H-1B visas for Design Engineers and has a consistent track record of doing so across its U.S. design centers and fabs. Sponsorship is standard practice for this function at Micron rather than a case-by-case exception. Roles in memory circuit design, physical design, and process integration are among those that have received H-1B filings.
How do I apply for Design Engineer jobs at Micron Technology?
Apply directly through Micron's careers portal and filter by engineering discipline and location. Roles in Boise, Milpitas, and Atlanta are the most active for Design Engineers. You can also use Migrate Mate to browse Micron Design Engineer openings that are tagged for visa sponsorship, which saves time identifying which postings are relevant if you need work authorization.
Which visa types does Micron Technology use for Design Engineer roles?
Micron sponsors H-1B and H-1B1 visas for Design Engineers at the nonimmigrant stage. For permanent residence, the company files PERM-based EB-2 and EB-3 Green Card petitions. H-1B1 is available only to Chilean and Singaporean nationals and does not require lottery participation, which makes it a faster path for eligible candidates already inside or outside the U.S.
What qualifications does Micron look for in sponsored Design Engineer candidates?
Micron typically expects a bachelor's or master's degree in electrical engineering, computer engineering, or a closely related discipline. Hands-on experience with circuit design, physical implementation, or memory architecture is valued at all levels. For H-1B eligibility, USCIS requires the role to qualify as a specialty occupation, meaning a degree in a specific technical field is a genuine job requirement, not just preferred.
How long does the visa sponsorship process take for a Micron Design Engineer offer?
If you are transitioning from OPT or CPT, your H-1B petition would typically target an October 1 start date, with USCIS registration in March. Standard adjudication runs three to five months. Premium processing, which USCIS offers for an additional fee, reduces adjudication to roughly 15 business days and is commonly used for Design Engineer hires when start dates are fixed.