Design Engineer Jobs at Cadence Design Systems with Visa Sponsorship
Design Engineer jobs at Cadence Design Systems span EDA software, IP development, and silicon verification, with a consistent track record of sponsoring work visas for technical roles in this function. If you're targeting a hardware or design-focused career in the U.S., Cadence is one of the more accessible paths.
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Get Access To All JobsINTRODUCTION
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
ABOUT THE JOB
The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.
The Cadence SSG Team is hiring graduates to join our R&D teams in San Jose, CA. This is an amazing opportunity to work as a Design Engineering Intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great SSG Team where you can make an impact that is visible.
This Design Engineering Intern position involves working on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product.
(a) Digital Design projects involve working on aspects of the logic design of the Janus NoC. It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.
(b) Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.
The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.
BASIC QUALIFICATIONS
- Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
- Deep understanding of Digital Design and/or Design Verification Fundamentals
- Excellent automation skills using Tcl, Perl, shell scripting
- Excellent oral and written communications skills
- Exposure to design automation tools is a plus
- Internship will be based in San Jose location. Ideal candidates should be from local school near office.
COMPENSATION
- The annual salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
We’re doing work that matters. Help us solve what others can’t.
INTRODUCTION
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
ABOUT THE JOB
The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.
The Cadence SSG Team is hiring graduates to join our R&D teams in San Jose, CA. This is an amazing opportunity to work as a Design Engineering Intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great SSG Team where you can make an impact that is visible.
This Design Engineering Intern position involves working on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product.
(a) Digital Design projects involve working on aspects of the logic design of the Janus NoC. It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.
(b) Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.
The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.
BASIC QUALIFICATIONS
- Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
- Deep understanding of Digital Design and/or Design Verification Fundamentals
- Excellent automation skills using Tcl, Perl, shell scripting
- Excellent oral and written communications skills
- Exposure to design automation tools is a plus
- Internship will be based in San Jose location. Ideal candidates should be from local school near office.
COMPENSATION
- The annual salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
We’re doing work that matters. Help us solve what others can’t.
See all Design Engineer Jobs at Cadence Design Systems
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Engineer Jobs at Cadence Design Systems.
Get Access To All JobsTips for Finding Design Engineer Jobs at Cadence Design Systems
Align your degree to Cadence's specialty occupation standard
H-1B approval for Design Engineers at Cadence hinges on demonstrating a direct link between your degree field and the specific role. A degree in electrical engineering, computer engineering, or a closely related discipline strengthens that tie considerably.
Target roles inside Cadence's core EDA product lines
Cadence's highest-volume Design Engineer hiring clusters around verification, analog design, and physical design for its core tooling. Applying to roles tied to Virtuoso, Spectre, or Genus positions your application in teams with established sponsorship workflows.
Request confirmation of LCA filing before accepting an offer
Before countersigning an offer, confirm that your employer has initiated the Labor Condition Application with DOL. Cadence's legal team typically handles this, but knowing the LCA is in motion protects your start-date planning.
Prepare your portfolio around functional verification or layout
Cadence interviewers assess Design Engineers on hands-on tool experience, not just academic credentials. Document specific projects involving RTL design, DRC clean-up, or simulation workflows, as these map directly to the specialty occupation criteria USCIS evaluates.
Use Migrate Mate to filter open Design Engineer roles by sponsorship type
Cadence posts Design Engineer openings across multiple teams simultaneously. Use Migrate Mate to filter listings specifically by H-1B or Green Card sponsorship so you spend time only on roles where your visa situation is already accounted for.
Account for PERM timing if you're building toward permanent residence
Cadence sponsors EB-2 and EB-3 Green Cards for Design Engineers, but PERM labor certification adds significant time to the permanent residence timeline. Starting that conversation with your hiring manager and HR during offer negotiation, not after onboarding, prevents gaps in planning.
Frequently Asked Questions
Does Cadence Design Systems sponsor H-1B visas for Design Engineers?
Yes, Cadence Design Systems sponsors H-1B visas for Design Engineers. The company has a dedicated immigration legal function that handles petitions for technical roles, and Design Engineering falls squarely within the specialty occupation classifications USCIS recognizes. If you're on OPT or a transferable H-1B, Cadence is an employer worth prioritizing in your search.
How do I apply for Design Engineer jobs at Cadence Design Systems?
Applications go through Cadence's careers portal, where Design Engineer roles are listed by product line and location. To find only the roles that include visa sponsorship, browse Migrate Mate, which filters Cadence's open positions by sponsorship type. Having a portfolio that demonstrates experience with EDA tools, RTL, or analog design gives your application the best foundation.
Which visa types does Cadence Design Systems typically use for Design Engineers?
Cadence sponsors both H-1B nonimmigrant visas and employment-based Green Cards, primarily EB-2 and EB-3, for Design Engineers. H-1B is the most common starting point for candidates already in the U.S. on OPT or a prior visa. Green Card sponsorship through PERM labor certification is available for longer-tenured employees on an established immigration track.
What qualifications does Cadence Design Systems expect from Design Engineer candidates?
Cadence typically expects a bachelor's or master's degree in electrical engineering, computer engineering, or a closely related field for Design Engineer roles. Hands-on experience with EDA tools such as those in Cadence's own product suite, RTL coding, analog circuit design, or physical verification carries significant weight. Industry internships or published research in hardware design can strengthen borderline applications.
How do I time my application around the H-1B cap and Cadence's hiring cycle?
USCIS opens H-1B registration in early March each year, with the cap lottery running shortly after. To be cap-eligible by October 1, you need a signed offer and a filed petition by April. Cadence's recruiting cycle for Design Engineers is most active in late summer and fall, so targeting applications three to four months before the March registration window gives you the best alignment.