Design Engineer Jobs at Intel with Visa Sponsorship
Design Engineer jobs at Intel span silicon architecture, physical design, RTL development, and verification across products like CPUs, GPUs, and network silicon. Intel has a well-established sponsorship track record for engineering roles and works with international candidates across multiple visa categories, including both employment-based and training-based pathways.
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About The Role
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness. In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
What You’ll Do
Key responsibilities will include but not limited to:
- Developing layout design methodology for testchip development in next generation process nodes
- Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
- Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
- Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
- Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
- Working with tool/flow owners and vendors for ongoing tool/methodology improvement
Behavioral Traits That We Are Looking For
- Exhibiting strong interest in Layout design in advanced technology nodes.
- Strong verbal and written communication skills
- Ability to work well both autonomously and in an intensive, cooperative team environment
- Coordinate between different stakeholders for testchip to arrive at execution commit for testchip
- Motivation to continuously learn and drive to push improved layout productivity and efficiency
Why Join Us
- Work on cutting-edge semiconductor technologies that shape the future of computing
- Collaborate with industry-leading experts across design and manufacturing
- Opportunities for career growth and technical leadership
- Contribute to innovations that impact global technology at scale
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note
For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information
Minimum Qualifications And Experience
Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:
- Experience with physical/layout design in advance technology nodes
- In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
- Design rules and layout constraints in advanced semiconductor processes
- Experience with floorplanning, hierarchical design integration, and layout verification/debug
Preferred Qualifications And Experience
- Experience in Definition of Testchip/Product design from Concept to Execution Commit
- Experience in working with Foundry teams on negotiating features to exercise in design
- Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
- Previous related work experience in a semiconductor foundry preferred
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
US, Texas, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
- Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Details
About The Role
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness. In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
What You’ll Do
Key responsibilities will include but not limited to:
- Developing layout design methodology for testchip development in next generation process nodes
- Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
- Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
- Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
- Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
- Working with tool/flow owners and vendors for ongoing tool/methodology improvement
Behavioral Traits That We Are Looking For
- Exhibiting strong interest in Layout design in advanced technology nodes.
- Strong verbal and written communication skills
- Ability to work well both autonomously and in an intensive, cooperative team environment
- Coordinate between different stakeholders for testchip to arrive at execution commit for testchip
- Motivation to continuously learn and drive to push improved layout productivity and efficiency
Why Join Us
- Work on cutting-edge semiconductor technologies that shape the future of computing
- Collaborate with industry-leading experts across design and manufacturing
- Opportunities for career growth and technical leadership
- Contribute to innovations that impact global technology at scale
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note
For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information
Minimum Qualifications And Experience
Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:
- Experience with physical/layout design in advance technology nodes
- In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
- Design rules and layout constraints in advanced semiconductor processes
- Experience with floorplanning, hierarchical design integration, and layout verification/debug
Preferred Qualifications And Experience
- Experience in Definition of Testchip/Product design from Concept to Execution Commit
- Experience in working with Foundry teams on negotiating features to exercise in design
- Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
- Previous related work experience in a semiconductor foundry preferred
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
US, Texas, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
- Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
See all 36+ Design Engineer Jobs at Intel
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Get Access To All JobsTips for Finding Design Engineer Jobs at Intel
Align your portfolio to Intel's silicon stack
Intel recruits Design Engineers for specific nodes and toolchains. Tailor your resume to show hands-on experience with RTL design, physical implementation, or DFT in contexts that map to CPU, GPU, or networking silicon, not generic FPGA or academic projects.
Target roles that match your visa category
Intel sponsors across H-1B, E-3, TN, and F-1 OPT. If you're on OPT, filter for teams with active projects since STEM OPT extensions require continuous employment. Use Migrate Mate to browse open Design Engineer positions filtered by sponsorship type.
Clarify the LCA wage level during offer negotiation
Intel files a Labor Condition Application with DOL for every sponsored hire. The prevailing wage level on your LCA must match your offered salary. Asking your recruiter which wage level the role is benchmarked at helps you catch mismatches before your I-129 is filed.
Build depth in Intel's interview loop early
Intel's Design Engineer hiring involves multiple technical screens covering microarchitecture, timing closure, or verification methodology depending on the team. Candidates who clear early rounds but lack depth in the specific design domain often stall at the hiring manager stage.
Confirm cap-exempt status if switching from academia
If you're transitioning from a university research role, Intel can file your H-1B outside the annual lottery if your previous employer was cap-exempt. Verify with USCIS guidelines whether a concurrent arrangement preserves that status during the transition period.
Prepare degree equivalency documentation before your offer letter
Intel's Design Engineer roles require a bachelor's or higher in electrical engineering or computer engineering. If your degree is from outside the U.S., a credential evaluation from a NACES-approved agency should be ready before USCIS adjudicates your specialty occupation petition.
Frequently Asked Questions
Does Intel sponsor H-1B visas for Design Engineers?
Yes, Intel sponsors H-1B visas for Design Engineer roles. Intel has a well-established internal immigration team that manages the full petition process, including the Labor Condition Application with DOL and the I-129 filing with USCIS. Because Intel participates in the H-1B lottery, timing your application to the annual registration window in March matters if you don't already hold H-1B visa status.
How do I apply for Design Engineer jobs at Intel?
Applications go through Intel's careers portal at intel.com/jobs. Search for Design Engineer roles filtered by product group or location. For roles that require sponsorship, the job posting typically indicates eligibility. Migrate Mate lists Intel's open Design Engineer positions and filters by visa sponsorship type, which saves time if you need to confirm a role supports your specific visa category before applying.
Which visa types does Intel commonly sponsor for Design Engineer roles?
Intel sponsors Design Engineers on H-1B, E-3 visa (for Australian citizens), TN visa (for Canadian and Mexican nationals), F-1 OPT and CPT for students, J-1 visa for interns and trainees, and employment-based Green Card pathways including EB-2 and EB-3. The applicable category depends on your nationality, education level, and career stage. Full-time hires most commonly proceed on H-1B or E-3 visa, with Green Card sponsorship typically initiated after a period of employment.
What qualifications does Intel expect for sponsored Design Engineer roles?
Intel's Design Engineer positions generally require a bachelor's degree or higher in electrical engineering, computer engineering, or a directly related field. For USCIS specialty occupation purposes, the degree must align with the specific role, so a computer science degree supporting a physical design role may require additional documentation. Hands-on experience with industry-standard EDA tools, HDL languages, or specific design flows strengthens both your candidacy and your petition.
How do I time a visa sponsorship filing with Intel's hiring process?
If you need H-1B sponsorship and don't currently hold that status, Intel would need to register you in the USCIS lottery held each March for an October 1 start date. If you're on OPT, Intel can hire you immediately and file for H-1B in the next cycle. E-3 and TN sponsors don't face a lottery and can be filed year-round, giving those candidates more scheduling flexibility.