Manufacturing Engineer Jobs at Astera Labs with Visa Sponsorship
Manufacturing Engineer roles at Astera Labs sit at the intersection of semiconductor design and high-volume production, translating cutting-edge connectivity silicon into manufacturable hardware. Astera Labs has a consistent track record of sponsoring work visas for engineering talent, making it a realistic target for international candidates in this field.
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Get Access To All JobsINTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ROLE AND RESPONSIBILITIES
As an Astera Labs Physical Design/CAD Engineer, you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.
- As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
- Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
- Architect and recommend flow improvements and enhance existing methodology for high performance design.
- Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
- Work with cross function teams to define requirements and specifications to achieve best PPA.
- Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity.
- Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.
BASIC QUALIFICATIONS
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
- 2-8 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Strong scripting ability (Tcl, Python, Perl).
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
PREFERRED EXPERIENCE
- Knowledge of agentic AI solutions is a plus.
- Experience working with EDA/IP vendors for both RTL and hard-macro integration.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
LOCATION
Location: San Jose, California, United States
INTRODUCTION
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
ROLE AND RESPONSIBILITIES
As an Astera Labs Physical Design/CAD Engineer, you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.
- As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
- Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
- Architect and recommend flow improvements and enhance existing methodology for high performance design.
- Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
- Work with cross function teams to define requirements and specifications to achieve best PPA.
- Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity.
- Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.
BASIC QUALIFICATIONS
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
- 2-8 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Strong scripting ability (Tcl, Python, Perl).
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
PREFERRED EXPERIENCE
- Knowledge of agentic AI solutions is a plus.
- Experience working with EDA/IP vendors for both RTL and hard-macro integration.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
LOCATION
Location: San Jose, California, United States
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Get Access To All JobsTips for Finding Manufacturing Engineer Jobs at Astera Labs Jobs
Tailor your resume to process engineering
Astera Labs hires Manufacturing Engineers to bridge chip design and production at scale. Highlight experience with DFM, yield analysis, or PCBA processes. Generic hardware resumes get screened out before sponsorship conversations even start.
Verify your OPT STEM extension eligibility early
Astera Labs is E-Verify enrolled, which is required for the 24-month STEM OPT extension. Confirm your degree field qualifies under the DHS STEM designated degree program list before your standard OPT window closes.
Target roles tied to active product ramps
Astera Labs Manufacturing Engineer openings tend to cluster around new product introduction cycles. Positions tied to active ramps move faster through offer and sponsorship approval than backfill roles, so timing your application to product launch signals matters.
Prepare documentation showing specialty occupation fit
For H-1B filing, USCIS scrutinizes whether the role genuinely requires a specialized degree. Gather job descriptions, your transcripts, and any employer correspondence that ties your specific engineering discipline directly to the Manufacturing Engineer position requirements.
Use Migrate Mate to filter active openings by visa type
Manufacturing Engineer roles at Astera Labs that include sponsorship are not always labeled consistently across job boards. Use Migrate Mate to filter Astera Labs openings by the specific visa types they actively sponsor for this function.
Manufacturing Engineer at Astera Labs jobs are hiring across the US. Find yours.
Find Manufacturing Engineer at Astera Labs JobsFrequently Asked Questions
Does Astera Labs sponsor H-1B visas for Manufacturing Engineers?
Yes, Astera Labs sponsors H-1B visas for Manufacturing Engineers. The company operates in semiconductor connectivity hardware, a field where specialized engineering talent is routinely sourced internationally. H-1B sponsorship for this function is part of their standard hiring practice, though the H-1B cap lottery applies if you are not already in H-1B status or cap-exempt.
How do I apply for Manufacturing Engineer jobs at Astera Labs?
Applications go through Astera Labs' careers page, where Manufacturing Engineer openings are posted as they become available. You can also browse and filter their active visa-sponsoring roles on Migrate Mate, which surfaces positions by sponsorship type. Tailor your application to highlight DFM, NPI, or process yield experience that maps directly to semiconductor hardware manufacturing.
Which visa types does Astera Labs commonly use for Manufacturing Engineers?
Astera Labs sponsors H-1B and Green Card pathways including EB-2 and EB-3 for Manufacturing Engineers, along with F-1 OPT and STEM OPT for recent graduates. TN status is available for Canadian and Mexican nationals whose engineering degree aligns with the USMCA engineer category. The right visa type depends on your citizenship, degree field, and how long you need authorization.
What qualifications does Astera Labs expect for Manufacturing Engineer roles?
Astera Labs Manufacturing Engineer roles typically require a bachelor's degree or higher in Electrical Engineering, Mechanical Engineering, or a closely related discipline. Hands-on experience with semiconductor or PCB manufacturing processes, familiarity with DFM principles, and exposure to NPI workflows are consistently valued. Advanced degrees strengthen both your candidacy and the specialty occupation case required for H-1B petitions.
How do I manage the timing between my job offer and H-1B filing at Astera Labs?
H-1B cap-subject petitions can only be filed for an October 1 start date, with the lottery registration window opening in March. If you receive an offer outside that window, Astera Labs may bridge your employment using F-1 OPT, STEM OPT, or another status. Aligning your offer timeline with the USCIS registration period reduces the risk of a gap in work authorization.
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