Ic Design Engineer Jobs in San Jose, CA
Ic Design Engineer jobs in San Jose, California are concentrated in Silicon Valley's core corridors, from North San Jose and Alviso to Milpitas and the broader Great Mall area, with demand driven by semiconductor, fabless chip design, and consumer electronics firms. Employers hiring right now include Cadence Design Systems, Cisco, and Broadcom. Find a role that fits below and apply directly.
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INTRODUCTION
Teradar is pioneering a new era in perception with the world’s first automotive terahertz vision sensor, delivering ultra-high resolution imaging in any weather condition. Founded in Boston, Teradar’s solid-state, chip-scale technology unlocks safer, smarter vehicles and opens the door to transformative applications in mobility, defense, and beyond.
ROLE AND RESPONSIBILITIES
You will lead the development of critical low-power AMS circuits, defining the clocking, PLL, and data converter architectures that power our novel terahertz sensor. This is a high-impact role where you will collaborate across RF, systems, and digital teams to bring next-generation sensor SoCs from initial concept to high-volume silicon.
- Architectural Leadership: Lead the definition and design of low-jitter clocking architectures, high-speed PLLs, and data converter signal chains, ensuring seamless integration with RF front-ends and digital back-ends.
- Circuit Design: Design and implement high-performance, low-power blocks including frequency-synthesized PLLs, VCOs, telemetric/diagnostic ADCs, programmable gain amplifiers (PGAs), bandgap references, and bias circuits.
- System Integration: Derive block-level specifications from complex system requirements and spearhead architecture-level trade-off discussions regarding noise, jitter, and power distribution.
- Full Lifecycle Ownership: Own the schematic design, pre-/post-layout simulation, and rigorous verification of clocking and data converter subsystems using industry-standard EDA tools.
- Physical Design Oversight: Work closely with layout engineers to ensure robust, noise-immune, and area-efficient physical implementations of jitter-sensitive circuits.
- Silicon Bring-up: Lead silicon validation, debugging, and characterization of clocking networks and ADCs in the lab to ensure hardware meets performance targets.
BASIC QUALIFICATIONS
- System Expertise: Proven experience in AMS design specifically for low-jitter clock generation (PLLs) and data conversion (ADCs) architectures. Deep understanding of frequency synthesis and signal conditioning.
- Experience: 10+ years of hands-on experience in analog and mixed-signal IC design, specifically in advanced nodes (e.g., TSMC 28nm or below).
- Block Expertise: Deep technical expertise in PLLs (integer/fractional-N, LC/Ring VCOs), high-precision or telemetry ADCs, PGAs, bandgap design, and biasing circuits.
- Tools: High proficiency with Cadence Virtuoso, Spectre, SpectreRF, and AMS simulation environments.
- Low-Power Mastery: Solid background in low-power design methodologies and the jitter/power trade-offs inherent in sensor clocking applications.
- Education: PhD in Electrical Engineering (or equivalent) preferred; MS required with significant industry track record.
LOCATION
* San Jose, CA (hybrid)
INTRODUCTION
Teradar is pioneering a new era in perception with the world’s first automotive terahertz vision sensor, delivering ultra-high resolution imaging in any weather condition. Founded in Boston, Teradar’s solid-state, chip-scale technology unlocks safer, smarter vehicles and opens the door to transformative applications in mobility, defense, and beyond.
ROLE AND RESPONSIBILITIES
You will lead the development of critical low-power AMS circuits, defining the clocking, PLL, and data converter architectures that power our novel terahertz sensor. This is a high-impact role where you will collaborate across RF, systems, and digital teams to bring next-generation sensor SoCs from initial concept to high-volume silicon.
- Architectural Leadership: Lead the definition and design of low-jitter clocking architectures, high-speed PLLs, and data converter signal chains, ensuring seamless integration with RF front-ends and digital back-ends.
- Circuit Design: Design and implement high-performance, low-power blocks including frequency-synthesized PLLs, VCOs, telemetric/diagnostic ADCs, programmable gain amplifiers (PGAs), bandgap references, and bias circuits.
- System Integration: Derive block-level specifications from complex system requirements and spearhead architecture-level trade-off discussions regarding noise, jitter, and power distribution.
- Full Lifecycle Ownership: Own the schematic design, pre-/post-layout simulation, and rigorous verification of clocking and data converter subsystems using industry-standard EDA tools.
- Physical Design Oversight: Work closely with layout engineers to ensure robust, noise-immune, and area-efficient physical implementations of jitter-sensitive circuits.
- Silicon Bring-up: Lead silicon validation, debugging, and characterization of clocking networks and ADCs in the lab to ensure hardware meets performance targets.
BASIC QUALIFICATIONS
- System Expertise: Proven experience in AMS design specifically for low-jitter clock generation (PLLs) and data conversion (ADCs) architectures. Deep understanding of frequency synthesis and signal conditioning.
- Experience: 10+ years of hands-on experience in analog and mixed-signal IC design, specifically in advanced nodes (e.g., TSMC 28nm or below).
- Block Expertise: Deep technical expertise in PLLs (integer/fractional-N, LC/Ring VCOs), high-precision or telemetry ADCs, PGAs, bandgap design, and biasing circuits.
- Tools: High proficiency with Cadence Virtuoso, Spectre, SpectreRF, and AMS simulation environments.
- Low-Power Mastery: Solid background in low-power design methodologies and the jitter/power trade-offs inherent in sensor clocking applications.
- Education: PhD in Electrical Engineering (or equivalent) preferred; MS required with significant industry track record.
LOCATION
* San Jose, CA (hybrid)
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Find Ic Design Engineer JobsIc Design Engineer Job Market in San Jose
Who's Hiring
- Cadence Design Systems10
- Cisco7
- Broadcom7
- Cadence3
- Teradar3
Top Industries Hiring
- Electronics & Hardware16
- Technology & Software10
- Science & Research3
Ic Design Engineer Jobs in San Jose: Frequently Asked Questions
How do I get a ic design engineer job in San Jose?
Focus your search on San Jose's semiconductor and fabless chip design ecosystem, which is denser here than almost anywhere else in the country. Employers in North San Jose, the Alviso corridor, and nearby Milpitas cluster heavily around analog, mixed-signal, and digital IC roles. Candidates with tape-out experience, proficiency in Cadence or Synopsys toolchains, and familiarity with advanced process nodes stand out in this market.
Which companies hire ic design engineers in San Jose?
Employers hiring ic design engineers in San Jose right now include Cadence Design Systems, Cisco, and Broadcom, based on current listings on Migrate Mate as of August 2026. San Jose's local market skews toward established semiconductor firms, fabless startups, and IP licensing companies, many of which maintain dedicated design centers within the city itself.
Are there remote ic design engineer jobs in San Jose?
Yes, though with meaningful limits, since IC design work often requires access to secure EDA tool licenses, lab hardware, and tape-out environments that are difficult to replicate remotely. About 33% of ic design engineer openings tied to San Jose are remote or hybrid as of August 2026. Verification, documentation, and some front-end RTL work tend to offer the most scheduling flexibility in San Jose roles.
How can I get a ic design engineer job in San Jose with little or no experience?
The most realistic entry path in San Jose is targeting design validation or physical design support roles at mid-size fabless companies, which are more open to junior hires than large established chipmakers. San Jose-area firms regularly recruit from nearby universities and often post internship-to-hire pipelines. Building hands-on experience with open-source VLSI tools, contributing to academic tape-out projects, and targeting roles like layout engineer or design verification engineer gives early-career candidates a concrete foothold.
Which industries hire the most ic design engineers in San Jose?
Most ic design engineer openings in San Jose sit in Electronics & Hardware, Technology & Software, and Science & Research, per current listings on Migrate Mate as of August 2026. San Jose's position as the geographic center of Silicon Valley means semiconductor development, consumer electronics hardware, and wireless communications infrastructure collectively drive the bulk of local hiring for this role.
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