Logic Design Engineer Jobs
Logic Design Engineer jobs are open across semiconductor, defense, consumer electronics, and EDA software companies, from new-grad to principal and staff levels, with specializations in RTL design, FPGA development, and verification. Find a role that fits below and apply directly.
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Showing 5 of 28+ Logic Design Engineer jobs
About Positron AI
Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.
Role Overview
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.
Key Responsibilities
Microarchitecture & RTL Leadership:
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
Technical Ownership & Signoff:
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
Advanced Interface & Memory Integration:
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Engage with IP vendors and internal stakeholders to ensure seamless integration.
Methodology & Best Practices:
- Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
- Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.
Cross-Functional Collaboration:
- Partner closely with Verification to define test plans and reference models.
- Work with Architecture and Performance teams to correlate models against RTL.
- Support bring-up, post-silicon debug, and customer engagements as required.
Mentorship & Technical Leadership:
- Guide junior engineers in design techniques, methodology, and problem-solving.
- Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions.
Required Qualifications
- BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven track record of leading designs from spec microarchitecture RTL signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
- Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
- Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
- Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.
Preferred Qualifications
- Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).
- Formal verification/SVA expertise for property checking and design assertions.
- Experience with low-power design techniques (clock-/power-gating, UPF/CPF).
- Collaboration experience with cocotb/UVM for checkers and reference model co-development.
- Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Why Join Us?
- Shape the next generation of AI inference hardware with a high-caliber, collaborative team.
- Take technical ownership of critical silicon components that directly impact product success.
- Competitive salary + equity, comprehensive benefits, and flexible work environment.
- Opportunities to innovate, lead, and grow your influence in a rapidly evolving space.
Compensation and Benefits
The base salary range for this role is $200,000 – $300,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.
About Positron AI
Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.
Role Overview
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.
Key Responsibilities
Microarchitecture & RTL Leadership:
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
Technical Ownership & Signoff:
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
Advanced Interface & Memory Integration:
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Engage with IP vendors and internal stakeholders to ensure seamless integration.
Methodology & Best Practices:
- Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
- Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.
Cross-Functional Collaboration:
- Partner closely with Verification to define test plans and reference models.
- Work with Architecture and Performance teams to correlate models against RTL.
- Support bring-up, post-silicon debug, and customer engagements as required.
Mentorship & Technical Leadership:
- Guide junior engineers in design techniques, methodology, and problem-solving.
- Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions.
Required Qualifications
- BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven track record of leading designs from spec microarchitecture RTL signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
- Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
- Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
- Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.
Preferred Qualifications
- Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).
- Formal verification/SVA expertise for property checking and design assertions.
- Experience with low-power design techniques (clock-/power-gating, UPF/CPF).
- Collaboration experience with cocotb/UVM for checkers and reference model co-development.
- Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Why Join Us?
- Shape the next generation of AI inference hardware with a high-caliber, collaborative team.
- Take technical ownership of critical silicon components that directly impact product success.
- Competitive salary + equity, comprehensive benefits, and flexible work environment.
- Opportunities to innovate, lead, and grow your influence in a rapidly evolving space.
Compensation and Benefits
The base salary range for this role is $200,000 – $300,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.
See All 28 Logic Design Engineer Jobs
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Find Logic Design Engineer JobsLogic Design Engineer Job Market
Who's Hiring
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
What Employers Look For
The qualifications that appear most often in logic design engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Proficiency in Verilog or VHDL for RTL design and simulation
- Experience with industry EDA tools for synthesis, simulation, and static timing analysis
- Familiarity with FPGA or ASIC design flows from RTL through place-and-route
- Understanding of digital design fundamentals including finite state machines, pipelining, and clock domain crossing
- Experience writing or reviewing functional verification testbenches and interpreting coverage reports
Tips for Your Logic Design Engineer Job Search
Tailor your resume for RTL-specific roles
Hiring managers for logic design roles scan resumes for specific hardware description languages like VHDL or Verilog. List the languages you've used, the design sizes you've worked on in gates or LUTs, and the EDA toolchains you know by vendor name.
Highlight synthesis and timing closure work
Many logic design engineer candidates undersell post-synthesis experience. Explicitly describe timing closure challenges you've solved, the tools you used to analyze critical paths, and whether your work targeted FPGAs, ASICs, or both.
Apply early to roles that fit
Migrate Mate lists logic design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by design abstraction level
Job titles vary widely: some postings want gate-level netlist experience while others focus on microarchitecture or IP integration. Read the responsibilities section carefully and prioritize listings that match the abstraction level where your strongest hands-on work lives.
Prepare a design walkthrough for technical screens
Expect at least one stage where you walk an interviewer through a design you built from spec to verified RTL. Practice explaining your partitioning decisions, your approach to testbench coverage, and any timing or resource trade-offs you made out loud.
Negotiate around tape-out and tapeout cycles
Offer timing in logic design can shift around active tape-out windows. If an offer comes during a crunch cycle, it's reasonable to ask whether start-date flexibility exists and to confirm that onboarding access to EDA licenses won't be delayed by the schedule.
Logic Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most logic design engineers?
Rambus, Hewlett Packard Enterprise | HPE, and Intel Corporation are hiring the most logic design engineers right now, with openings concentrated in California, Oregon, and Texas, based on current listings on Migrate Mate as of November 2026. Demand is especially active at companies developing custom silicon, defense electronics, and next-generation FPGA platforms.
How many logic design engineer jobs are remote?
About 80% of logic design engineer openings are fully remote or hybrid as of November 2026, reflecting the hands-on lab and EDA license access that many design teams require on-site. Roles focused on RTL coding, documentation, and pre-silicon verification tend to offer the most remote flexibility compared to positions tied to physical lab bring-up.
How do you become a logic design engineer?
Start with a degree in electrical or computer engineering with coursework in digital logic, computer architecture, and HDL-based design. Build hands-on experience through capstone projects, open-source FPGA work, or internships that expose you to RTL coding and simulation. Proficiency in at least one major EDA toolchain and experience closing timing on a real design are what move candidates from coursework to job-ready.
How do you get hired as a logic design engineer with little experience?
Focus on building a concrete design portfolio rather than relying on coursework descriptions alone. Implement a small processor, a custom peripheral, or an interface controller on an FPGA development board, document your RTL decisions, and push the project to a public repository. Applying to associate or junior-level roles that emphasize learning under a senior designer is more effective than chasing senior titles before your portfolio is ready.
What does the logic design engineer interview process look like?
Most processes start with a recruiter screen followed by a technical phone interview covering digital fundamentals such as finite state machines, setup and hold timing, and metastability. A coding or design exercise in Verilog or VHDL typically comes next, either take-home or live. Final rounds usually include a system design discussion and a walkthrough of past work where interviewers probe your reasoning on partitioning, verification strategy, and trade-offs.
Where can I find and apply to logic design engineer jobs?
You can find and apply to logic design engineer jobs on Migrate Mate, which lists current openings from companies across the United States. Search the listings to find roles that match your experience level and design focus, then apply directly to each one that fits.
See All 28 Logic Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find Logic Design Engineer Jobs