Physical Design Engineer Jobs in Santa Clara, CA
Physical Design Engineer jobs in Santa Clara are concentrated in the central business corridors along Central Expressway and the Great America Parkway area, with strong demand across semiconductor IP, fabless chip design, and EDA tooling. Employers hiring right now include Qualcomm, Apple, and Tenstorrent. See the openings below and apply to the ones that match your experience.
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Showing 5 of 84+ Physical Design Engineer jobs
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
This individual independently plans, performs the moderately-defined responsibility for the Physical Design Flow of high-speed DDR, graphics, physical verification flows, microarchitecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings.
Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
Pay Range: $146,717.00 - $190,100.00/year
Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
If you would like more information about this role, please contact Qualcomm Careers .
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
This individual independently plans, performs the moderately-defined responsibility for the Physical Design Flow of high-speed DDR, graphics, physical verification flows, microarchitecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings.
Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
Pay Range: $146,717.00 - $190,100.00/year
Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
If you would like more information about this role, please contact Qualcomm Careers .
See All 84 Physical Design Engineer Jobs in Santa Clara
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Find Physical Design Engineer JobsPhysical Design Engineer Job Market in Santa Clara
Who's Hiring
- Qualcomm23
- Apple14
- Tenstorrent14
- NVIDIA9
- Astera Labs9
Top Industries Hiring
- Electronics & Hardware42
- Technology & Software19
- Telecommunications9
Physical Design Engineer Jobs in Santa Clara: Frequently Asked Questions
How do I get a physical design engineer job in Santa Clara?
Focus your search on Santa Clara's dense concentration of fabless semiconductor companies, EDA vendors, and chip IP firms clustered around Great America Parkway and the Central Expressway corridor. Hands-on experience with place-and-route tools, timing closure, and low-power design gives candidates a clear edge here. Targeting companies with active tape-out pipelines and networking through local IEEE Santa Clara Valley chapter events are both practical moves in this market.
Which companies hire physical design engineers in Santa Clara?
Santa Clara physical design engineer roles are posted by Qualcomm, Apple, and Tenstorrent and others right now, based on current listings on Migrate Mate as of August 2026. Santa Clara attracts a mix of large semiconductor corporations, mid-size fabless design houses, and EDA software companies, all with ongoing demand for physical design talent.
Are there remote physical design engineer jobs in Santa Clara?
Yes, though with limits, since physical design engineering often requires access to licensed EDA tools, secure design environments, and close collaboration during tape-out cycles. About 40% of physical design engineer openings tied to Santa Clara are remote or hybrid as of August 2026, with remote options most common in early-stage floorplanning and constraint definition rather than hands-on signoff work.
How can I get a physical design engineer job in Santa Clara with little or no experience?
The most realistic entry path is targeting layout or physical verification roles at mid-size fabless companies in Santa Clara, where teams are smaller and new engineers get broader exposure faster than at large corporations. Internships at EDA vendors or chip startups around the Great America Parkway area regularly convert to full-time roles. Building proficiency in Cadence Innovus or Synopsys ICC2 and contributing to academic or open-source RTL-to-GDS projects strengthens any entry-level application considerably.
Which industries hire the most physical design engineers in Santa Clara?
Most physical design engineer openings in Santa Clara sit in Electronics & Hardware, Technology & Software, and Telecommunications, per current listings on Migrate Mate as of August 2026. Santa Clara's role as the geographic heart of Silicon Valley means semiconductor design and EDA software development drive the bulk of local hiring, supported by a tight cluster of companies that depends on physical design expertise for every product cycle.
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