Physical Design Engineer Jobs in Santa Clara, CA
Physical Design Engineer jobs in Santa Clara are concentrated in the central business corridors along Central Expressway and the Great America Parkway area, with strong demand across semiconductor IP, fabless chip design, and EDA tooling. Employers hiring right now include Qualcomm, AMD, and Tenstorrent. See the openings below and apply to the ones that match your experience.
Find Physical Design Engineer JobsOverview
Open roles91
Top employerQualcomm
Work type58% On-site
Top credentialBachelor's degree in electrical engineering
Companies hiring9
Showing 5 of 91+ Physical Design Engineer jobs
Senior Physical Design Engineer
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Added 5d ago
AMD
Senior Physical Design Engineer
Santa Clara, California
Added 5d ago
Physical Design and Timing Engineer Intern - Summer 2027
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Added 1w ago
NVIDIA
Physical Design and Timing Engineer Intern - Summer 2027
Santa Clara, California
Added 1w ago
CPU Server Physical Design Engineer
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Added 2w ago
Qualcomm
CPU Server Physical Design Engineer
Santa Clara, California
Added 2w ago
Physical Design Engineer Intern, BS - Summer 2027
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Added 3w ago
Marvell Technology
Physical Design Engineer Intern, BS - Summer 2027
Santa Clara, California
Added 3w ago
Physical Design Engineer Intern, MS - Summer 2027
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Added 3w ago
Marvell Technology
Physical Design Engineer Intern, MS - Summer 2027
Santa Clara, California
Added 3w ago
Added 5d ago
Senior Physical Design Engineer
AMD·Santa Clara, California
Job functions:
Hybrid
Bachelor's degree in electrical engineering
5,001-10,000 employees
Job Description
Overview:
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
Responsibilities:
THE ROLE:
THE PERSON:
KEY RESPONSIBLITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
This role is not eligible for visa sponsorship.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
Join a team developing next-generation AI and high-performance computing silicon. In this role, you will lead and contribute to advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff, and design optimization across block, subsystem, and chip-level designs. Working closely with architecture, RTL, CAD, technology, and product engineering teams, you will help deliver high-quality silicon while advancing methodology, automation, and data-driven design solutions that improve power, performance, and area (PPA).
THE PERSON:
You are a hands-on physical design expert with a strong track record of solving complex implementation and timing challenges on advanced-node designs. You combine deep technical expertise with the ability to provide technical leadership, influence design decisions, mentor engineers, and collaborate effectively across globally distributed teams. You are detail-oriented, highly analytical, and thrive in fast-paced environments where ownership and innovation are valued.
KEY RESPONSIBLITIES:
- Lead physical design activities across block, subsystem, and chip-level implementations.
- Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
- Develop and enhance physical design methodologies, design flows, and automation solutions.
- Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
- Define and execute engineering change (ECO) strategies throughout implementation and signoff.
- Support formal verification, physical verification, and tapeout preparation activities.
- Analyze design data and trends to improve design quality, predictability, and efficiency.
- Collaborate with cross-functional engineering teams to achieve successful silicon delivery.
- Contribute to AI-assisted and machine learning-driven design optimization initiatives.
- Troubleshoot complex implementation challenges and develop scalable technical solutions.
PREFERRED EXPERIENCE:
- Experience with ASIC physical design, implementation, and timing closure.
- Experience working across block, subsystem, and chip-level design environments.
- Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
- Experience with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus.
- Experience with timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal.
- Advanced-node semiconductor design experience, including leading-edge process technologies.
- Strong scripting and automation skills using TCL, Python, Perl, Pandas, or similar technologies.
- Experience developing design flows, methodologies, and productivity-enhancing automation.
- Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows.
- Experience with data analysis, database technologies, and design-quality metrics.
ACADEMIC CREDENTIALS:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.
This role is not eligible for visa sponsorship.
#LI-LC3
#LI-HYBRID
Qualifications:
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
AMD
Senior Physical Design Engineer
Santa Clara, California
Added 5d ago5,001-10,000 employees
Job functions:
Hybrid
Bachelor's degree in electrical engineering
Job Description
Overview:
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
Responsibilities:
THE ROLE:
THE PERSON:
KEY RESPONSIBLITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
This role is not eligible for visa sponsorship.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
Join a team developing next-generation AI and high-performance computing silicon. In this role, you will lead and contribute to advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff, and design optimization across block, subsystem, and chip-level designs. Working closely with architecture, RTL, CAD, technology, and product engineering teams, you will help deliver high-quality silicon while advancing methodology, automation, and data-driven design solutions that improve power, performance, and area (PPA).
THE PERSON:
You are a hands-on physical design expert with a strong track record of solving complex implementation and timing challenges on advanced-node designs. You combine deep technical expertise with the ability to provide technical leadership, influence design decisions, mentor engineers, and collaborate effectively across globally distributed teams. You are detail-oriented, highly analytical, and thrive in fast-paced environments where ownership and innovation are valued.
KEY RESPONSIBLITIES:
- Lead physical design activities across block, subsystem, and chip-level implementations.
- Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
- Develop and enhance physical design methodologies, design flows, and automation solutions.
- Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
- Define and execute engineering change (ECO) strategies throughout implementation and signoff.
- Support formal verification, physical verification, and tapeout preparation activities.
- Analyze design data and trends to improve design quality, predictability, and efficiency.
- Collaborate with cross-functional engineering teams to achieve successful silicon delivery.
- Contribute to AI-assisted and machine learning-driven design optimization initiatives.
- Troubleshoot complex implementation challenges and develop scalable technical solutions.
PREFERRED EXPERIENCE:
- Experience with ASIC physical design, implementation, and timing closure.
- Experience working across block, subsystem, and chip-level design environments.
- Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
- Experience with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus.
- Experience with timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal.
- Advanced-node semiconductor design experience, including leading-edge process technologies.
- Strong scripting and automation skills using TCL, Python, Perl, Pandas, or similar technologies.
- Experience developing design flows, methodologies, and productivity-enhancing automation.
- Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows.
- Experience with data analysis, database technologies, and design-quality metrics.
ACADEMIC CREDENTIALS:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.
This role is not eligible for visa sponsorship.
#LI-LC3
#LI-HYBRID
Qualifications:
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
See All 91 Physical Design Engineer Jobs in Santa Clara
Find roles in Santa Clara that match your experience and apply in just a few clicks.
Find Physical Design Engineer JobsPhysical Design Engineer Job Market in Santa Clara
Who's Hiring
- Qualcomm22
- AMD13
- Tenstorrent13
- Apple9
- NVIDIA9
Top Industries Hiring
- Electronics & Hardware35
- Technology & Software22
- Telecommunications13
Physical Design Engineer Jobs in Santa Clara: Frequently Asked Questions
How do I get a physical design engineer job in Santa Clara?
Focus your search on Santa Clara's dense concentration of fabless semiconductor companies, EDA vendors, and chip IP firms clustered around Great America Parkway and the Central Expressway corridor. Hands-on experience with place-and-route tools, timing closure, and low-power design gives candidates a clear edge here. Targeting companies with active tape-out pipelines and networking through local IEEE Santa Clara Valley chapter events are both practical moves in this market.
Which companies hire physical design engineers in Santa Clara?
Santa Clara physical design engineer roles are posted by Qualcomm, AMD, and Tenstorrent and others right now, based on current listings on Migrate Mate as of September 2026. Santa Clara attracts a mix of large semiconductor corporations, mid-size fabless design houses, and EDA software companies, all with ongoing demand for physical design talent.
Are there remote physical design engineer jobs in Santa Clara?
Yes, though with limits, since physical design engineering often requires access to licensed EDA tools, secure design environments, and close collaboration during tape-out cycles. About 42% of physical design engineer openings tied to Santa Clara are remote or hybrid as of September 2026, with remote options most common in early-stage floorplanning and constraint definition rather than hands-on signoff work.
How can I get a physical design engineer job in Santa Clara with little or no experience?
The most realistic entry path is targeting layout or physical verification roles at mid-size fabless companies in Santa Clara, where teams are smaller and new engineers get broader exposure faster than at large corporations. Internships at EDA vendors or chip startups around the Great America Parkway area regularly convert to full-time roles. Building proficiency in Cadence Innovus or Synopsys ICC2 and contributing to academic or open-source RTL-to-GDS projects strengthens any entry-level application considerably.
Which industries hire the most physical design engineers in Santa Clara?
Most physical design engineer openings in Santa Clara sit in Electronics & Hardware, Technology & Software, and Telecommunications, per current listings on Migrate Mate as of September 2026. Santa Clara's role as the geographic heart of Silicon Valley means semiconductor design and EDA software development drive the bulk of local hiring, supported by a tight cluster of companies that depends on physical design expertise for every product cycle.
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See All 91 Physical Design Engineer Jobs in Santa Clara
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