Physical Design Engineer Jobs
Physical Design Engineer jobs are open across semiconductor, consumer electronics, automotive, and defense industries, from entry-level to principal and staff engineer, with specializations in floorplanning, timing closure, and power integrity. Find a role that fits below and apply directly.
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Company: Quest Global Services-N.A., Inc.
Position Title: Physical Design Lead Engineer
Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client
locations throughout the U.S.
Position Responsibilities:
Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced process nodes (3nm or below). Take care of floor-planning, CTS (Clock Tree Synthesis), Route use ICC2, Innovus tools related to Cadence and Synopsys. Optimize design with multi-corner multi-mode (MCMM) timing constraint. Fix setup, hold, transition, capacitance, crosstalk violation, min pulse width (MPW), signal EM (Electromigration)
and solving congestion, short, skew, etc. Work on high-speed and complicated clock structure designs with a large number of memories and instances. Use PrimeTime to check and debug timing. Analyze floorplan to reduce congestion using advanced scripting techniques generate a robust clock tree by analyzing the sync points and achieving low latency and minimal power. Work on Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, Power. Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM. Build ECO environments for place and route tools to fix all timing violations. Work on
Power Analysis and IR Drop Analysis to meet the requirements. Work on Physical Verification
(PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS), Antenna, Electrical Rule
Check (ERC), Design for Manufacturing (DFM). Work on logic equivalence check (LEC) for Pre-
Post Place and Route design.
Position Requirements:
Bachelor’s degree (or foreign equivalent) in Electronics Engineering, or a
related field, PLUS five (5) years of experience in the job offered or a related position. Experience
must include demonstrable knowledge of: The full Place & Route design flow incl. logical
synthesis, STA, DFT, Placement, Clock Tree Synthesis & physical verification; hardening highspeed,
low power CPU designs; design of large SOC full chip & block level P&R using advance
Process technologies: advanced process nodes (3nm or below); high-speed interfaces at chip level;
clock tree creation incl. sync points & achieving low latency & minimal power; design w/ multicorner
multi-mode timing constraints; STA; control of timing budget between blocks & chip using
timing model such as ETM, ILM; ECO environments for place & route tools to fix timing
violations. Travel to unanticipated client locations throughout the U.S., approximately 30%, as
required. May telecommute from any location within the U.S.
Apply at careers.quest-global.com and reference Job Code 28290.0330
Pay Range: $130,333 - $160,000
Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.
Company: Quest Global Services-N.A., Inc.
Position Title: Physical Design Lead Engineer
Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client
locations throughout the U.S.
Position Responsibilities:
Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced process nodes (3nm or below). Take care of floor-planning, CTS (Clock Tree Synthesis), Route use ICC2, Innovus tools related to Cadence and Synopsys. Optimize design with multi-corner multi-mode (MCMM) timing constraint. Fix setup, hold, transition, capacitance, crosstalk violation, min pulse width (MPW), signal EM (Electromigration)
and solving congestion, short, skew, etc. Work on high-speed and complicated clock structure designs with a large number of memories and instances. Use PrimeTime to check and debug timing. Analyze floorplan to reduce congestion using advanced scripting techniques generate a robust clock tree by analyzing the sync points and achieving low latency and minimal power. Work on Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, Power. Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM. Build ECO environments for place and route tools to fix all timing violations. Work on
Power Analysis and IR Drop Analysis to meet the requirements. Work on Physical Verification
(PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS), Antenna, Electrical Rule
Check (ERC), Design for Manufacturing (DFM). Work on logic equivalence check (LEC) for Pre-
Post Place and Route design.
Position Requirements:
Bachelor’s degree (or foreign equivalent) in Electronics Engineering, or a
related field, PLUS five (5) years of experience in the job offered or a related position. Experience
must include demonstrable knowledge of: The full Place & Route design flow incl. logical
synthesis, STA, DFT, Placement, Clock Tree Synthesis & physical verification; hardening highspeed,
low power CPU designs; design of large SOC full chip & block level P&R using advance
Process technologies: advanced process nodes (3nm or below); high-speed interfaces at chip level;
clock tree creation incl. sync points & achieving low latency & minimal power; design w/ multicorner
multi-mode timing constraints; STA; control of timing budget between blocks & chip using
timing model such as ETM, ILM; ECO environments for place & route tools to fix timing
violations. Travel to unanticipated client locations throughout the U.S., approximately 30%, as
required. May telecommute from any location within the U.S.
Apply at careers.quest-global.com and reference Job Code 28290.0330
Pay Range: $130,333 - $160,000
Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.
Physical Design Engineer Jobs by Experience Level
Top Cities Hiring Physical Design Engineers
Explore physical design engineer openings in the cities hiring most right now.
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Find Physical Design Engineer JobsPhysical Design Engineer Job Market
Who's Hiring
- Apple37
- Qualcomm13
- NVIDIA10
- Astera Labs7
- Kimley-Horn7
Top Industries Hiring
- Electronics & Hardware63
- Technology & Software25
- Consulting & Professional Services24
- Telecommunications5
- Aerospace & Defense5
What Employers Look For
The qualifications that appear most often in physical design engineer jobs.
- Experience with industry-standard EDA tools such as Synopsys IC Compiler or Cadence Innovus
- Hands-on work with advanced process nodes at 7nm, 5nm, or below
- Proficiency in static timing analysis and timing closure methodologies
- Strong scripting skills in Tcl, Python, or Perl for flow automation
- Bachelor's or master's degree in electrical engineering or computer engineering
- Familiarity with physical verification tools including DRC and LVS sign-off
Tips for Your Physical Design Engineer Job Search
Tailor your resume to the node
List the specific process nodes you have worked on, whether 7nm, 5nm, or 28nm, because hiring managers filter instantly on this. A resume that buries node experience in a summary rather than a skills section will get passed over.
Quantify your timing closure wins
Recruiters and engineers reviewing your resume want to see that you closed timing on a real tapeout, not just ran scripts. State the block size, frequency target, and number of violations you resolved to give your experience concrete weight.
Target openings by tool stack match
Physical design roles frequently require specific EDA tools like Synopsys IC Compiler, Cadence Innovus, or Mentor Calibre. Match your application to postings where your tool experience overlaps at least two of the listed requirements to improve your callback rate.
Apply early to roles that fit
Migrate Mate lists physical design engineer openings from across the United States in one place, so you can find roles that match your node and tool experience and apply directly to each listing.
Prepare for a hands-on design exercise
Many physical design interviews include a whiteboard or take-home exercise on floorplanning constraints or clock tree synthesis. Practice explaining your design decisions out loud, because interviewers care as much about your reasoning as your final answer.
Negotiate using tapeout ownership not years
When discussing compensation, anchor your case to the number of tapeouts you owned end-to-end and the complexity of blocks you closed, not total years of experience. Ownership of a full chip flow at an advanced node carries more leverage than seniority alone.
Physical Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most physical design engineers?
The companies hiring the most physical design engineers right now include Apple, Qualcomm, and NVIDIA, with the largest share of openings in California, Texas, and Oregon, based on current listings on Migrate Mate as of August 2026. Demand is concentrated at companies running active tapeout programs at advanced nodes.
How many physical design engineer jobs are remote?
About 34% of physical design engineer openings are fully remote or hybrid as of August 2026, though on-site roles remain dominant given the tool licensing, server access, and lab proximity the work often requires. Sub-areas like script development, methodology, and flow automation tend to have the highest share of remote-eligible postings.
How do you become a physical design engineer?
Start with a bachelor's degree in electrical or computer engineering, with coursework in VLSI design, digital circuits, and semiconductor devices. Build hands-on skills in at least one major EDA tool through coursework, internships, or personal projects. Move into an entry-level role focused on place-and-route or physical verification, then progress toward owning full blocks and eventually full chip tapeouts across successive projects.
Can you get a physical design engineer job with little experience?
Entry-level physical design engineer roles exist, but you need demonstrable tool exposure to get past the first screen. A senior design project, university chip fabrication program, or an internship where you ran place-and-route on even a small block gives you something concrete to discuss. Roles labeled associate or junior engineer are the most accessible starting points and often provide structured mentorship on a running tapeout team.
What does the physical design engineer interview process look like?
Most processes include an initial recruiter screen, a technical phone interview covering fundamentals like clock tree synthesis, timing constraints, and floorplanning, and then one or more on-site or virtual rounds with senior engineers. Expect at least one design exercise or case study where you walk through a physical implementation decision. Final rounds often include a hiring manager conversation focused on tapeout ownership and cross-functional collaboration.
Where can I find and apply to physical design engineer jobs?
You can find and apply to physical design engineer jobs on Migrate Mate, which lists current openings from across the United States in one place. Find roles that match your node experience, tool skills, and seniority level, then apply directly to each listing that fits.
See All 216+ Physical Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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