Physical Design Engineer Jobs
Physical Design Engineer jobs are open across semiconductor, consumer electronics, automotive, and defense industries, from entry-level to principal and staff engineer, with specializations in floorplanning, timing closure, and power integrity. Find a role that fits below and apply directly.
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Showing 5 of 240+ Physical Design Engineer jobs
About the Company:
At SK hynix memory solutions, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in NAND flash technology and memory solutions, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix memory solutions, you will be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
About the Role
Join our Physical Design(SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance, Area) while ensuring silicon success. This role requires deep hands-on expertise across the full physical design flow as well as leadership to mentor junior engineers and define methodologies for the team.
Responsibilities
- Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced process nodes (7nm, 5nm, 3nm)
- Execute and optimize synthesis, placement, clock tree synthesis (CTS), and routing using industry-standard P&R tools (Synopsys ICC2/Fusion Compiler or Cadence Innovus)
- Drive timing closure and signoff using PrimeTime (PT), including advanced analysis such as SI, AOCV/POCV, crosstalk, and ECO implementation
- Perform RC extraction using StarRC or Quantus and ensure strong correlation between extraction and STA results
- Own physical verification signoff with Mentor/Siemens Calibre, resolving DRC, LVS, ERC, and antenna violations in complex FinFET layouts
- Conduct power integrity analysis using Ansys RedHawk(Redhawk-SC), including static/dynamic IR drop and EM analysis; implement power grid and decap optimizations
- Develop and maintain physical design flows and automation scripts (Tcl, Perl, Python), mentor junior engineers, and collaborate with cross-functional teams to achieve tapeout schedules
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred)
- 8+ years of hands-on experience in ASIC physical design with proven tapeout success
- Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools
- Deep knowledge of static timing analysis (STA) and PrimeTime signoff, including multi-corner/multi-mode closure
- Demonstrated experience with physical verification using Calibre (DRC, LVS, ERC) and IR drop/EM analysis using RedHawk
Preferred Qualifications
- Experience at 5nm or 3nm process nodes with FinFET and multi-patterning design rules
- Familiarity with low-power design techniques including UPF, clock gating, multi-Vt, and voltage islands
- Strong programming skills in Tcl, Perl, and Python for flow automation and data analysis
- Knowledge of ECO implementation and clock reconstruction (CRPR, useful skew) methodologies
- Experience leading or mentoring a team of physical design engineers on complex SoC projects
- Exposure to memory-centric interfaces and systems such as SSD SoC, HBM, or HBF (High Bandwidth Flash) base die designs (a plus, not required)
- Familiarity with chiplet and die-to-die (D2D) interconnect technologies, including Universal Chiplet Interconnect Express (UCIe) or equivalent D2D PHY protocols (a plus, not required)
COMPENSATION: $160,000/yr - $220,000/yr
REGARDING COMPENSATION:
SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
About the Company:
At SK hynix memory solutions, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in NAND flash technology and memory solutions, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix memory solutions, you will be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
About the Role
Join our Physical Design(SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance, Area) while ensuring silicon success. This role requires deep hands-on expertise across the full physical design flow as well as leadership to mentor junior engineers and define methodologies for the team.
Responsibilities
- Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced process nodes (7nm, 5nm, 3nm)
- Execute and optimize synthesis, placement, clock tree synthesis (CTS), and routing using industry-standard P&R tools (Synopsys ICC2/Fusion Compiler or Cadence Innovus)
- Drive timing closure and signoff using PrimeTime (PT), including advanced analysis such as SI, AOCV/POCV, crosstalk, and ECO implementation
- Perform RC extraction using StarRC or Quantus and ensure strong correlation between extraction and STA results
- Own physical verification signoff with Mentor/Siemens Calibre, resolving DRC, LVS, ERC, and antenna violations in complex FinFET layouts
- Conduct power integrity analysis using Ansys RedHawk(Redhawk-SC), including static/dynamic IR drop and EM analysis; implement power grid and decap optimizations
- Develop and maintain physical design flows and automation scripts (Tcl, Perl, Python), mentor junior engineers, and collaborate with cross-functional teams to achieve tapeout schedules
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred)
- 8+ years of hands-on experience in ASIC physical design with proven tapeout success
- Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools
- Deep knowledge of static timing analysis (STA) and PrimeTime signoff, including multi-corner/multi-mode closure
- Demonstrated experience with physical verification using Calibre (DRC, LVS, ERC) and IR drop/EM analysis using RedHawk
Preferred Qualifications
- Experience at 5nm or 3nm process nodes with FinFET and multi-patterning design rules
- Familiarity with low-power design techniques including UPF, clock gating, multi-Vt, and voltage islands
- Strong programming skills in Tcl, Perl, and Python for flow automation and data analysis
- Knowledge of ECO implementation and clock reconstruction (CRPR, useful skew) methodologies
- Experience leading or mentoring a team of physical design engineers on complex SoC projects
- Exposure to memory-centric interfaces and systems such as SSD SoC, HBM, or HBF (High Bandwidth Flash) base die designs (a plus, not required)
- Familiarity with chiplet and die-to-die (D2D) interconnect technologies, including Universal Chiplet Interconnect Express (UCIe) or equivalent D2D PHY protocols (a plus, not required)
COMPENSATION: $160,000/yr - $220,000/yr
REGARDING COMPENSATION:
SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
Physical Design Engineer Jobs by Experience Level
Top Cities Hiring Physical Design Engineers
Explore physical design engineer openings in the cities hiring most right now.
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Find Physical Design Engineer JobsPhysical Design Engineer Job Market
Who's Hiring
- Apple29
- Qualcomm15
- Kimley-Horn15
- Micron Technology12
- AMD8
Top Industries Hiring
- Electronics & Hardware48
- Consulting & Professional Services22
- Technology & Software20
- Telecommunications5
- Aerospace & Defense3
What Employers Look For
The qualifications that appear most often in physical design engineer jobs.
- Experience with industry-standard EDA tools such as Synopsys IC Compiler or Cadence Innovus
- Hands-on work with advanced process nodes at 7nm, 5nm, or below
- Proficiency in static timing analysis and timing closure methodologies
- Strong scripting skills in Tcl, Python, or Perl for flow automation
- Bachelor's or master's degree in electrical engineering or computer engineering
- Familiarity with physical verification tools including DRC and LVS sign-off
Tips for Your Physical Design Engineer Job Search
Tailor your resume to the node
List the specific process nodes you have worked on, whether 7nm, 5nm, or 28nm, because hiring managers filter instantly on this. A resume that buries node experience in a summary rather than a skills section will get passed over.
Quantify your timing closure wins
Recruiters and engineers reviewing your resume want to see that you closed timing on a real tapeout, not just ran scripts. State the block size, frequency target, and number of violations you resolved to give your experience concrete weight.
Target openings by tool stack match
Physical design roles frequently require specific EDA tools like Synopsys IC Compiler, Cadence Innovus, or Mentor Calibre. Match your application to postings where your tool experience overlaps at least two of the listed requirements to improve your callback rate.
Apply early to roles that fit
Migrate Mate lists physical design engineer openings from across the United States in one place, so you can find roles that match your node and tool experience and apply directly to each listing.
Prepare for a hands-on design exercise
Many physical design interviews include a whiteboard or take-home exercise on floorplanning constraints or clock tree synthesis. Practice explaining your design decisions out loud, because interviewers care as much about your reasoning as your final answer.
Negotiate using tapeout ownership not years
When discussing compensation, anchor your case to the number of tapeouts you owned end-to-end and the complexity of blocks you closed, not total years of experience. Ownership of a full chip flow at an advanced node carries more leverage than seniority alone.
Physical Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most physical design engineers?
The companies hiring the most physical design engineers right now include Apple, Qualcomm, and Kimley-Horn, with the largest share of openings in California, Texas, and Colorado, based on current listings on Migrate Mate as of September 2026. Demand is concentrated at companies running active tapeout programs at advanced nodes.
How many physical design engineer jobs are remote?
About 41% of physical design engineer openings are fully remote or hybrid as of September 2026, though on-site roles remain dominant given the tool licensing, server access, and lab proximity the work often requires. Sub-areas like script development, methodology, and flow automation tend to have the highest share of remote-eligible postings.
How do you become a physical design engineer?
Start with a bachelor's degree in electrical or computer engineering, with coursework in VLSI design, digital circuits, and semiconductor devices. Build hands-on skills in at least one major EDA tool through coursework, internships, or personal projects. Move into an entry-level role focused on place-and-route or physical verification, then progress toward owning full blocks and eventually full chip tapeouts across successive projects.
Can you get a physical design engineer job with little experience?
Entry-level physical design engineer roles exist, but you need demonstrable tool exposure to get past the first screen. A senior design project, university chip fabrication program, or an internship where you ran place-and-route on even a small block gives you something concrete to discuss. Roles labeled associate or junior engineer are the most accessible starting points and often provide structured mentorship on a running tapeout team.
What does the physical design engineer interview process look like?
Most processes include an initial recruiter screen, a technical phone interview covering fundamentals like clock tree synthesis, timing constraints, and floorplanning, and then one or more on-site or virtual rounds with senior engineers. Expect at least one design exercise or case study where you walk through a physical implementation decision. Final rounds often include a hiring manager conversation focused on tapeout ownership and cross-functional collaboration.
Where can I find and apply to physical design engineer jobs?
You can find and apply to physical design engineer jobs on Migrate Mate, which lists current openings from across the United States in one place. Find roles that match your node experience, tool skills, and seniority level, then apply directly to each listing that fits.
See All 240+ Physical Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find Physical Design Engineer Jobs