Mid Level Physical Design Engineer Jobs
Mid level physical design engineer jobs go to engineers ready to own implementation blocks end to end, make timing closure decisions with limited oversight, and guide junior team members through tapeout milestones. Openings are concentrated across Electronics & Hardware, Technology & Software, and Telecommunications, with employers like Apple, Qualcomm, and Mirafra Technologies competing for engineers at this level now.
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Showing 5 of 27+ Mid Level Physical Design Engineer jobs
Key Responsibilities
- Deeply understand what is involved in physical design
- Running PD flows to close blocks, support ASIC infrastructure, automate PD flows
- Improve CAD infrastructure
- Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
- Drive dashboards that show the convergence of projects related to PD
- Optimize tool flows, working with EDA vendors to incorporate the latest features
- Accountable for block level closure
- Supervise the outsourcing of physical design to a 3rd party service
You may be a good fit if you have
- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
- Deeply creative and able to think from first principles
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
Key Responsibilities
- Deeply understand what is involved in physical design
- Running PD flows to close blocks, support ASIC infrastructure, automate PD flows
- Improve CAD infrastructure
- Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
- Drive dashboards that show the convergence of projects related to PD
- Optimize tool flows, working with EDA vendors to incorporate the latest features
- Accountable for block level closure
- Supervise the outsourcing of physical design to a 3rd party service
You may be a good fit if you have
- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
- Deeply creative and able to think from first principles
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
See All 27 Mid Level Physical Design Engineer Jobs
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Find JobsMid Level Physical Design Engineer Job Market
Who's Hiring
- Apple10
- Qualcomm7
- Mirafra Technologies2
- AMD1
- Etched1
Top Industries Hiring
- Electronics & Hardware22
- Technology & Software8
- Telecommunications7
- Consulting & Professional Services3
- Retail1
Mid Level Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a mid level physical design engineer job?
Position your experience around ownership, not just task completion. Highlight specific blocks you drove through floorplan, place and route, and signoff, and name the process nodes and tools you know well. Recruiters at this level want to see that you've debugged real timing or DRC problems independently, so lead your resume with measurable outcomes from tapeouts or successful silicon rather than a list of responsibilities.
Which companies hire mid level physical design engineers?
Companies hiring mid level physical design engineers right now include Apple, Qualcomm, and Mirafra Technologies, based on current listings on Migrate Mate as of November 2026. Hiring at this level comes from semiconductor fabless companies, integrated device manufacturers, and large consumer electronics firms that run continuous tapeout cycles and need engineers who can own a block without heavy supervision.
Are there remote mid level physical design engineer jobs?
Yes, though the role is more commonly on-site or hybrid than fully remote given lab access and tapeout coordination needs. About 5% of mid level physical design engineer openings are remote or hybrid as of November 2026, so flexible arrangements do exist and are worth filtering for when you search current listings on Migrate Mate.
How do I move up to a mid level physical design engineer role?
The path from entry level to mid level centers on deepening tool fluency and taking progressive ownership. Early on, focus on mastering one or two key stages, such as place and route or static timing analysis, then seek out projects where you drive a full block rather than assisting. Demonstrating that you can identify and resolve closure issues without constant guidance, and contributing to a successful tapeout, is what signals readiness for mid level responsibility.
Which industries hire the most mid level physical design engineers?
Mid Level physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, based on current listings on Migrate Mate as of November 2026. These sectors drive the most hiring at this level because they operate aggressive chip development schedules that require experienced engineers who can own physical implementation work independently across multiple concurrent projects.