Mid Level Physical Design Engineer Jobs
Mid level physical design engineer jobs go to engineers ready to own implementation blocks end to end, make timing closure decisions with limited oversight, and guide junior team members through tapeout milestones. Openings are concentrated across Electronics & Hardware, Technology & Software, and Consulting & Professional Services, with employers like Kimley-Horn, Apple, and Qualcomm competing for engineers at this level now.
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Job title: Physical Design Engineer
Location: Austin, TX & Mountain View, CA
Job type: Full-time
Job Description
We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.
Key Responsibilities
- Drive block-level physical design implementation from netlist to GDSII.
- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
- Optimize designs for Power, Performance, and Area (PPA) targets.
- Achieve timing closure across multiple corners and modes.
- Analyze and resolve setup, hold, transition, capacitance, and noise violations.
- Develop and maintain timing constraints (SDC) and STA signoff methodologies.
- Perform EMIR (Electromigration & IR Drop) analysis and closure.
- Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
- Debug physical design issues and drive design convergence within project schedules.
Required Skills
Strong experience in Physical Design and PnR flow.
Hands-on expertise in:
- Floorplanning
- Placement & Optimization
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- Static Timing Analysis (STA)
- Timing Constraints (SDC)
- EMIR Analysis
- PPA Optimization
Experience with industry-standard EDA tools such as:
- Synopsys Fusion Compiler / ICC2
- PrimeTime
- Cadence Innovus (optional)
- RedHawk / Voltus (EMIR)
Good understanding of low-power design techniques and signoff methodologies.
Preferred Qualifications
- Bachelor's or Master's degree in Electrical/Electronics Engineering.
- Experience in advanced nodes (7nm/5nm/3nm preferred).
- Strong debugging and problem-solving skills.
- Experience working with cross-functional silicon teams.
Pay: $120,000.00 - $140,000.00 per year
Benefits:
- 401(k)
- Dental insurance
- Health insurance
- Life insurance
- Paid time off
- Relocation assistance
- Vision insurance
Work Location: In person
Job title: Physical Design Engineer
Location: Austin, TX & Mountain View, CA
Job type: Full-time
Job Description
We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.
Key Responsibilities
- Drive block-level physical design implementation from netlist to GDSII.
- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
- Optimize designs for Power, Performance, and Area (PPA) targets.
- Achieve timing closure across multiple corners and modes.
- Analyze and resolve setup, hold, transition, capacitance, and noise violations.
- Develop and maintain timing constraints (SDC) and STA signoff methodologies.
- Perform EMIR (Electromigration & IR Drop) analysis and closure.
- Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
- Debug physical design issues and drive design convergence within project schedules.
Required Skills
Strong experience in Physical Design and PnR flow.
Hands-on expertise in:
- Floorplanning
- Placement & Optimization
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- Static Timing Analysis (STA)
- Timing Constraints (SDC)
- EMIR Analysis
- PPA Optimization
Experience with industry-standard EDA tools such as:
- Synopsys Fusion Compiler / ICC2
- PrimeTime
- Cadence Innovus (optional)
- RedHawk / Voltus (EMIR)
Good understanding of low-power design techniques and signoff methodologies.
Preferred Qualifications
- Bachelor's or Master's degree in Electrical/Electronics Engineering.
- Experience in advanced nodes (7nm/5nm/3nm preferred).
- Strong debugging and problem-solving skills.
- Experience working with cross-functional silicon teams.
Pay: $120,000.00 - $140,000.00 per year
Benefits:
- 401(k)
- Dental insurance
- Health insurance
- Life insurance
- Paid time off
- Relocation assistance
- Vision insurance
Work Location: In person
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Who's Hiring
Top Industries Hiring
- Electronics & Hardware12
- Technology & Software7
- Consulting & Professional Services7
- Telecommunications3
- Retail2
Mid Level Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a mid level physical design engineer job?
Position your experience around ownership, not just task completion. Highlight specific blocks you drove through floorplan, place and route, and signoff, and name the process nodes and tools you know well. Recruiters at this level want to see that you've debugged real timing or DRC problems independently, so lead your resume with measurable outcomes from tapeouts or successful silicon rather than a list of responsibilities.
Which companies hire mid level physical design engineers?
Companies hiring mid level physical design engineers right now include Kimley-Horn, Apple, and Qualcomm, based on current listings on Migrate Mate as of September 2026. Hiring at this level comes from semiconductor fabless companies, integrated device manufacturers, and large consumer electronics firms that run continuous tapeout cycles and need engineers who can own a block without heavy supervision.
Are there remote mid level physical design engineer jobs?
Yes, though the role is more commonly on-site or hybrid than fully remote given lab access and tapeout coordination needs. About 21% of mid level physical design engineer openings are remote or hybrid as of September 2026, so flexible arrangements do exist and are worth filtering for when you search current listings on Migrate Mate.
How do I move up to a mid level physical design engineer role?
The path from entry level to mid level centers on deepening tool fluency and taking progressive ownership. Early on, focus on mastering one or two key stages, such as place and route or static timing analysis, then seek out projects where you drive a full block rather than assisting. Demonstrating that you can identify and resolve closure issues without constant guidance, and contributing to a successful tapeout, is what signals readiness for mid level responsibility.
Which industries hire the most mid level physical design engineers?
Mid Level physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, based on current listings on Migrate Mate as of September 2026. These sectors drive the most hiring at this level because they operate aggressive chip development schedules that require experienced engineers who can own physical implementation work independently across multiple concurrent projects.