Mid Level Physical Design Engineer Jobs
Mid level physical design engineer jobs go to engineers ready to own implementation blocks end to end, make timing closure decisions with limited oversight, and guide junior team members through tapeout milestones. Openings are concentrated across Electronics & Hardware, Technology & Software, and Telecommunications, with employers like Apple, Qualcomm, and Intel competing for engineers at this level now.
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Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and three (3) years of experience in a related occupation. Will also accept a Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and seven (7) years of progressive experience in a related occupation. Employer will accept any suitable combination of education, training or experience.
Pay Range: $161,179.00 - $210,000.00/year
Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
If you would like more information about this role, please contact Qualcomm Careers .
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Find JobsMid Level Physical Design Engineer Job Market
Who's Hiring
- Apple28
- Qualcomm8
- Intel3

- NVIDIA3
- Astera Labs3

Top Industries Hiring
- Electronics & Hardware50
- Technology & Software15
- Telecommunications7
- Consulting & Professional Services6
- Retail3
Mid Level Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a mid level physical design engineer job?
Position your experience around ownership, not just task completion. Highlight specific blocks you drove through floorplan, place and route, and signoff, and name the process nodes and tools you know well. Recruiters at this level want to see that you've debugged real timing or DRC problems independently, so lead your resume with measurable outcomes from tapeouts or successful silicon rather than a list of responsibilities.
Which companies hire mid level physical design engineers?
Companies hiring mid level physical design engineers right now include Apple, Qualcomm, and Intel, based on current listings on Migrate Mate as of July 2026. Hiring at this level comes from semiconductor fabless companies, integrated device manufacturers, and large consumer electronics firms that run continuous tapeout cycles and need engineers who can own a block without heavy supervision.
Are there remote mid level physical design engineer jobs?
Yes, though the role is more commonly on-site or hybrid than fully remote given lab access and tapeout coordination needs. About 13% of mid level physical design engineer openings are remote or hybrid as of July 2026, so flexible arrangements do exist and are worth filtering for when you search current listings on Migrate Mate.
How do I move up to a mid level physical design engineer role?
The path from entry level to mid level centers on deepening tool fluency and taking progressive ownership. Early on, focus on mastering one or two key stages, such as place and route or static timing analysis, then seek out projects where you drive a full block rather than assisting. Demonstrating that you can identify and resolve closure issues without constant guidance, and contributing to a successful tapeout, is what signals readiness for mid level responsibility.
Which industries hire the most mid level physical design engineers?
Mid Level physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, based on current listings on Migrate Mate as of July 2026. These sectors drive the most hiring at this level because they operate aggressive chip development schedules that require experienced engineers who can own physical implementation work independently across multiple concurrent projects.