Remote Physical Design Engineer Jobs
Remote Physical Design Engineer jobs are open across the semiconductor, EDA software, and fabless chip design sectors at remote-first firms and distributed engineering teams, from mid-level layout roles to principal and staff positions. Employers hiring remotely right now include K2 Space, Tenstorrent, and Nvidia. See the openings below and apply to the ones that match your experience.
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Showing 5 of 10+ Remote Physical Design Engineer jobs
Locations: San Jose, CA or Irvine, CA or remote
Core Responsibilities
- RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
- Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
- Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
- Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
- Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
- Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.
Key Qualifications
- Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
- Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
- Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).
- Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.
Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
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Who's Hiring
Top Industries Hiring
- Electronics & Hardware
- Consulting & Professional Services
What Employers Look For
The qualifications that appear most often in remote physical design engineer jobs.
- Experience with industry-standard EDA tools such as Synopsys IC Compiler or Cadence Innovus
- Hands-on work with advanced process nodes at 7nm, 5nm, or below
- Proficiency in static timing analysis and timing closure methodologies
- Strong scripting skills in Tcl, Python, or Perl for flow automation
- Bachelor's or master's degree in electrical engineering or computer engineering
- Familiarity with physical verification tools including DRC and LVS sign-off
Tips for Your Remote Physical Design Engineer Job Search
Apply early to remote roles that fit
Migrate Mate lists remote physical design engineer openings from across the U.S. in one place, so you can find roles matched to your PnR and timing closure experience and apply directly without sifting through unrelated postings.
Document async contributions in your portfolio
Remote employers can't observe your process, so show it. Publish floorplan decisions, congestion maps, and timing closure reports with written rationale. Async-readable documentation signals you can operate without hand-holding across time zones.
Get fluent in remote-native EDA workflows
Distributed physical design teams run Innovus, ICC2, and Calibre over cloud or VPN-accessible servers. Demonstrate that you've used these tools in a remote compute environment, not just a lab workstation, because remote employers ask about it directly.
Screen for distributed team structure before applying
Check whether the engineering team is actually distributed or whether the role is remote by exception. Fabless companies and EDA vendors with async-first engineering culture are far more likely to give remote physical design engineers full project ownership from the start.
Remote Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a remote physical design engineer job?
Target remote-first semiconductor companies, fabless chip startups, and EDA tool vendors that run fully distributed engineering teams. Remote employers screen hard for demonstrated proficiency in place-and-route tools like Innovus or ICC2, and they weight written communication and self-directed project management heavily because there's no one to ask over your shoulder. A public portfolio of floorplanning or timing closure work gives you a concrete edge.
Which companies hire remote physical design engineers?
Employers currently hiring remote physical design engineers include K2 Space, Tenstorrent, and Nvidia, per current remote listings on Migrate Mate as of August 2026. Remote openings for this role are concentrated at fabless semiconductor companies, EDA software firms, and chip IP vendors that operate distributed engineering teams across multiple time zones.
Can you get a remote physical design engineer job with no experience?
Yes, but remote entry-level roles are harder to land because employers expect you to troubleshoot PnR and timing closure issues independently from day one. Smaller fabless startups and EDA vendors are the most likely to hire entry-level remotely. Academic tape-out projects, open-source PDK work, and Skywater shuttle chips all serve as concrete proof of hands-on skills when professional experience is limited.
Do you need a degree for remote physical design engineer jobs?
Usually, but demonstrated hands-on skills carry significant weight alongside a degree. Most remote employers in the semiconductor and EDA space do list a BS in electrical engineering or a related field, but candidates who can show verified tape-out experience, strong PnR tool proficiency, and clean timing signoff results are competitive even when their academic background is unconventional.
Which industries hire the most remote physical design engineers?
The sectors hiring the most remote physical design engineers are Electronics & Hardware and Consulting & Professional Services, based on current remote listings on Migrate Mate as of August 2026. Those sectors rely on distributed teams of physical design specialists who contribute to chip development cycles without needing to be co-located with fab or design center staff.
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