Senior Level Physical Design Engineer Jobs
Senior level physical design engineer jobs place engineers in charge of full-chip implementation, floorplan ownership, and the cross-functional decisions that determine whether a design closes on time and on spec. Openings are concentrated in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, with a mix of on-site, hybrid, and remote roles, and employers like Apple, Intel, and Micron Technology hiring at this level now.
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Showing 5 of 108+ Senior Level Physical Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
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Find JobsSenior Level Physical Design Engineer Job Market
Who's Hiring
- Apple33
- Intel11
- Micron Technology6
- Qualcomm5
- Tenstorrent5
Top Industries Hiring
- Electronics & Hardware78
- Technology & Software18
- Consulting & Professional Services11
- Telecommunications4
- Artificial Intelligence4
Senior Level Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level physical design engineer job?
Employers at this level expect more than execution. They look for engineers who have owned a full implementation flow from floorplan through signoff, navigated competing constraints across power, performance, and area, and can defend their decisions in design reviews. Candidates who have mentored junior engineers or led a small implementation team consistently stand out, as do those with deep expertise in advanced-node design rules and timing closure at scale.
Which companies hire senior level physical design engineers?
Companies hiring senior level physical design engineers right now include Apple, Intel, and Micron Technology, based on current listings on Migrate Mate as of July 2026. Hiring at this level covers semiconductor companies, fabless chip designers, and major technology firms building custom silicon for data center, mobile, and automotive applications.
Are there remote senior level physical design engineer jobs?
Yes, though physical design work still skews toward on-site due to EDA tool licensing, compute infrastructure, and lab collaboration requirements. About 25% of senior level physical design engineer openings are remote or hybrid as of July 2026, so candidates seeking flexibility will find options, particularly at companies with distributed engineering organizations or strong remote EDA infrastructure.
What makes a physical design engineer role senior level?
A senior level role is defined by scope and ownership, not just task complexity. Senior engineers own entire blocks or full-chip implementation, make architectural decisions that affect downstream teams, and are accountable for meeting PPA targets without close supervision. They are expected to mentor junior and mid-level engineers, resolve cross-domain conflicts between physical design and design verification or DFT teams, and drive the implementation strategy for a project from concept through tapeout.
Which industries hire the most senior level physical design engineers?
Senior level physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, based on current listings on Migrate Mate as of July 2026. These sectors drive hiring because they are developing or acquiring custom silicon at scale, where the complexity of modern process nodes demands engineers with the depth and ownership capability that senior roles require.