Senior Level Physical Design Engineer Jobs
Senior level physical design engineer jobs place engineers in charge of full-chip implementation, floorplan ownership, and the cross-functional decisions that determine whether a design closes on time and on spec. Openings are concentrated in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, with a mix of on-site, hybrid, and remote roles, and employers like Apple, Tenstorrent, and Cisco hiring at this level now.
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INTRODUCTION
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.
Key Responsibilities
- Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
- Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
- Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
- Drive agentic AI development initiatives and develop AI/LLM driven workflows.
BASIC QUALIFICATIONS
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
- Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
- Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
- Experience implementing AI flows and using agentic AI and LLMs.
PREFERRED QUALIFICATIONS
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 15 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
COMPENSATION
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$177,000.00 - $309,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
INTRODUCTION
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.
Key Responsibilities
- Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
- Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
- Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
- Drive agentic AI development initiatives and develop AI/LLM driven workflows.
BASIC QUALIFICATIONS
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
- Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
- Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
- Experience implementing AI flows and using agentic AI and LLMs.
PREFERRED QUALIFICATIONS
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 15 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
COMPENSATION
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$177,000.00 - $309,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
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Find JobsSenior Level Physical Design Engineer Job Market
Who's Hiring
- Apple16
- Tenstorrent3
- Cisco2
- Eliyan2
- NVIDIA2
Top Industries Hiring
- Electronics & Hardware28
- Technology & Software9
- Consulting & Professional Services7
- Aerospace & Defense2
- Education1
Senior Level Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level physical design engineer job?
Employers at this level expect more than execution. They look for engineers who have owned a full implementation flow from floorplan through signoff, navigated competing constraints across power, performance, and area, and can defend their decisions in design reviews. Candidates who have mentored junior engineers or led a small implementation team consistently stand out, as do those with deep expertise in advanced-node design rules and timing closure at scale.
Which companies hire senior level physical design engineers?
Companies hiring senior level physical design engineers right now include Apple, Tenstorrent, and Cisco, based on current listings on Migrate Mate as of September 2026. Hiring at this level covers semiconductor companies, fabless chip designers, and major technology firms building custom silicon for data center, mobile, and automotive applications.
Are there remote senior level physical design engineer jobs?
Yes, though physical design work still skews toward on-site due to EDA tool licensing, compute infrastructure, and lab collaboration requirements. About 24% of senior level physical design engineer openings are remote or hybrid as of September 2026, so candidates seeking flexibility will find options, particularly at companies with distributed engineering organizations or strong remote EDA infrastructure.
What makes a physical design engineer role senior level?
A senior level role is defined by scope and ownership, not just task complexity. Senior engineers own entire blocks or full-chip implementation, make architectural decisions that affect downstream teams, and are accountable for meeting PPA targets without close supervision. They are expected to mentor junior and mid-level engineers, resolve cross-domain conflicts between physical design and design verification or DFT teams, and drive the implementation strategy for a project from concept through tapeout.
Which industries hire the most senior level physical design engineers?
Senior level physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, based on current listings on Migrate Mate as of September 2026. These sectors drive hiring because they are developing or acquiring custom silicon at scale, where the complexity of modern process nodes demands engineers with the depth and ownership capability that senior roles require.