Design Verification Jobs
Design Verification jobs are open across semiconductors, aerospace, automotive, and consumer electronics, from entry-level to principal and staff engineer, with specializations in functional verification, formal methods, and hardware-software integration. Find a role that fits from the openings below and apply directly.
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Showing 5 of 282+ Design Verification jobs
INTRODUCTION
Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency. We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers. This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.
ROLE AND RESPONSIBILITIES
- Self motivated personality with a strong presence to do things right.
- Need to have a strong sense of teamwork and ability to work well with others.
- Constrained random verification methodologies with experience driving completion via coverage closure.
- Preferable to have skills with SV and UVM, well versed in OOP.
TOOLS/LANGUAGES
- System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...).
BASIC QUALIFICATIONS
- Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience.
COMPENSATION AND BENEFITS
- The annual base salary range for this position is $129,400.00 - $207,000.00.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
INTRODUCTION
Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency. We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers. This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.
ROLE AND RESPONSIBILITIES
- Self motivated personality with a strong presence to do things right.
- Need to have a strong sense of teamwork and ability to work well with others.
- Constrained random verification methodologies with experience driving completion via coverage closure.
- Preferable to have skills with SV and UVM, well versed in OOP.
TOOLS/LANGUAGES
- System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...).
BASIC QUALIFICATIONS
- Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience.
COMPENSATION AND BENEFITS
- The annual base salary range for this position is $129,400.00 - $207,000.00.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Find Design Verification JobsDesign Verification Job Market
A snapshot from current openings nationwide, updated as new roles post.
Who's Hiring
- Apple112
- Google24
- Micron Idaho Semiconductor Manufacturing (Triton)11
- Qualcomm9
- GlobalFoundries8
Top Industries Hiring
- Electronics & Hardware203
- Technology & Software54
- Consulting & Professional Services11
- Artificial Intelligence9
- Manufacturing6
What Employers Look For
The qualifications that appear most often in design verification jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM-based verification environments
- Experience with industry-standard simulators such as Cadence Xcelium, Synopsys VCS, or Mentor Questa
- Hands-on functional coverage closure and assertion-based verification on RTL designs
- Familiarity with formal verification tools such as JasperGold or VC Formal
- Understanding of AMBA protocols including AXI, AHB, or APB for interface-level verification
Tips for Your Design Verification Job Search
Quantify coverage closure on your resume
Design verification resumes that list specific coverage metrics, assertion counts, or functional coverage results stand out immediately. Recruiters scanning for verification engineers want to see numbers tied to tape-out milestones, not just tool names or methodology buzzwords.
Lead with your simulation environment expertise
SystemVerilog UVM, Cadence Xcelium, and Synopsys VCS show up in nearly every job posting. Call out your primary simulation environment in your resume summary and match it to the exact tool stack listed in each job description before applying.
Filter openings by verification methodology
Job titles for this role vary widely, from verification engineer to design verification lead to SoC validation engineer. Search for the specific methodology you work in, such as formal verification or emulation, alongside the title to surface openings that actually match your background.
Apply early to roles that fit
Migrate Mate lists design verification openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Prepare for a live debug session in interviews
Most design verification interviews include a hands-on waveform or simulation debug exercise. Practice walking through a failing assertion or X-state propagation bug out loud, because interviewers assess your methodology and communication as much as your technical answer.
Negotiate based on tape-out experience
Candidates who have taken a block or full chip through tape-out can anchor compensation conversations around that milestone. When discussing offers, be specific about which process nodes you have verified on and the scope of coverage you owned end to end.
Design Verification Jobs: Frequently Asked Questions
Which companies are hiring the most design verifications?
The companies hiring the most design verifications right now include Apple, Google, and Micron Idaho Semiconductor Manufacturing (Triton), with the largest share of openings in California, Texas, and Oregon, based on current listings on Migrate Mate as of June 2026. Semiconductor IP vendors and vertically integrated chip teams tend to post the highest volume consistently.
How many design verification jobs are remote?
About 13% of design verification openings are fully remote or hybrid as of June 2026, with availability varying significantly by role type. Formal verification and coverage analysis work tends to be more remote-compatible, while emulation and lab-based silicon validation roles are more likely to require on-site presence.
How do you become a design verification engineer?
Start with a degree in electrical engineering, computer engineering, or computer science, then build hands-on skills in SystemVerilog and UVM through coursework, personal projects, or open-source RTL repositories. Get comfortable with at least one major simulator, write your own testbenches to exercise RTL designs, and practice closing functional coverage on small blocks before applying to entry-level roles.
Can you get a design verification job with little experience?
Yes, entry-level design verification roles exist, but you need to show verifiable hands-on work even without industry history. Build a portfolio of UVM testbenches on publicly available RTL designs, document coverage closure results, and highlight any FPGA or chip design coursework where you wrote assertions or caught RTL bugs. Internships at semiconductor companies are the fastest path to a first full-time offer.
What does the design verification interview process look like?
Most design verification interviews include a phone screen covering SystemVerilog fundamentals, followed by one or two technical rounds with live coding or waveform debug exercises. Later rounds typically involve a design discussion where you walk through a verification plan you have owned. Some companies add a take-home testbench assignment before the final hiring manager conversation.
Where can I find and apply to design verification jobs?
You can find and apply to design verification jobs on Migrate Mate, which lists current openings from across the United States. Search the listings to find roles that match your background and experience level, then apply directly to each one that fits.
See All 282+ Design Verification Jobs
Jump back to the full list of openings and apply to any design verification role that fits.
Find Design Verification Jobs