Senior Level Design Verification Jobs
Senior level design verification jobs put experienced engineers in charge of verification strategy, sign-off authority, and the teams or workstreams that execute complex validation across full chip and system-level designs. Roles cover 50% remote and hybrid arrangements across Electronics & Hardware, Technology & Software, and Artificial Intelligence, with employers like Apple, Google, and Tenstorrent hiring at this level now.
Find JobsOverview
Showing 5 of 25+ Senior Level Design Verification jobs











Would you like to join Apple’s growing wireless silicon development team? Our wireless SoC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering.
Description
In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.
Responsibilities
- Work closely with the system and design teams to review and understand the MAC subsystem microarchitecture, and create verification plan from specification, review and refine to achieve coverage targets.
- Build block/subsystem level test benches, create UVM libraries, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind.
- Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
- Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
- Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
- Support MAC subsystem validation using Palladium and/or FPGA.
- Work with team members to improve DV methodology and flow.
Minimum Qualifications
- BS and a minimum of 10 years relevant industry experience.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
- Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine.
Preferred Qualifications
- 7+ years of verification experience of wireless/wired communication block/subsystem.
- Verification experience of wireless/wired communication block/subsystem.
- Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
- Proficient in shell and Python scripting, Perl scripting.
- Experience of using AI technologies in data mining/analysis.
- Experience of Palladium/FPGA validation.
- Should be a team player with excellent communication skills, self-motivated and well organized.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
See All 25 Senior Level Design Verification Jobs
Find roles that match your experience and apply in just a few clicks.
Find JobsSenior Level Design Verification Job Market
Who's Hiring



Top Industries Hiring
- Electronics & Hardware11
- Technology & Software9
- Artificial Intelligence3
- Manufacturing1
- Aerospace & Defense1
Senior Level Design Verification Jobs: Frequently Asked Questions
How do I get a senior level design verification job?
Employers at this level want engineers who have owned verification plans end to end, not just executed tasks assigned by others. Demonstrated expertise in formal verification, UVM-based testbench architecture, or coverage closure on complex SoCs gives candidates a strong edge. Leadership signals matter too, such as mentoring junior engineers, driving methodology decisions, and presenting sign-off results to design and program teams.
Which companies hire senior level design verifications?
Companies hiring senior level design verifications right now include Apple, Google, and Tenstorrent, based on current listings on Migrate Mate as of November 2026. Hiring at this level tends to concentrate in semiconductor companies, EDA vendors, and large systems firms that run multi-year chip development programs requiring deep verification ownership.
Are there remote senior level design verification jobs?
Yes, though on-site and hybrid arrangements remain common given lab access and team collaboration demands. About 50% of senior level design verification openings are remote or hybrid as of November 2026, with fully remote roles more common at companies using distributed design teams or cloud-based simulation infrastructure.
What makes a design verification role senior level?
Senior level design verification roles are defined by ownership and scope rather than task execution. At this level, engineers lead the verification planning for a block, subsystem, or full chip, make methodology calls, and are accountable for coverage closure and sign-off readiness. Mentoring less experienced engineers and collaborating directly with design leads and program managers are also standard expectations.
Which industries hire the most senior level design verifications?
Senior Level design verification roles concentrate in Electronics & Hardware, Technology & Software, and Artificial Intelligence, based on current listings on Migrate Mate as of November 2026. These sectors drive hiring at this level because they run high-complexity silicon programs where verification depth and ownership directly affect product risk, tape-out schedules, and long-term platform reliability.