Senior Level Design Verification Jobs
Senior level design verification jobs put experienced engineers in charge of verification strategy, sign-off authority, and the teams or workstreams that execute complex validation across full chip and system-level designs. Roles cover 23% remote and hybrid arrangements across Electronics & Hardware, Technology & Software, and Artificial Intelligence, with employers like Apple, NVIDIA, and Google hiring at this level now.
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- Sunnyvale, CA, United States
- Not Remote
- Engineering
- JOB214493
Company Description
It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly 30 years later, that question still fuels everything we do at Intuitive. As a global leader in robotic-assisted surgery and minimally invasive care, our technologies—like the da Vinci surgical system and Ion—have transformed how care is delivered for millions of patients worldwide.
We’re a team of engineers, clinicians, and innovators united by one purpose: to make surgery smarter, safer, and more human. Every day, our work helps care teams perform with greater precision and patients recover faster, improving outcomes around the world.
The problems we solve demand creativity, rigor, and collaboration. The work is challenging, but deeply meaningful—because every improvement we make has the potential to change a life.
If you’re ready to contribute to something bigger than yourself and help transform the future of healthcare, you’ll find your purpose here.
Job Description
Roles & Responsibilities
- Verification of FPGA’s on daVinci systems for RTL functional correctness
- Starting from test-planning to closing verification using coverage metrics
- Hands-on testbench development UVM
- Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model
- Write constrained random stimulus and Implement functional cover groups
- Debugging failures, bug tracking, and analyze and close coverage
Qualifications
Required Education, Skills & Experience
- Advanced knowledge of HVL methodology (UVM)
- Expertise in HVL and HDL (SystemVerilog, Verilog)
- Experience defining coverage space and writing coverage models
- Team player with excellent communication skills and the desire to take on diverse challenges
- Experience writing scripts in languages such as Perl/Python
- Solid verification skills in problem solving, constrained random testing, and debugging
- Experience with Emulation/FPGA prototyping and Formal is a plus
- Experience with ML-assisted flows, and agentic-AI automation frameworks to accelerate coverage closure, improve debug efficiency, and enhance overall verification throughput
Additional Information
Due to the nature of our business and the role, please note that Intuitive and/or your customer(s) may require that you show current proof of vaccination against certain diseases including COVID-19. Details can vary by role.
Intuitive is an Equal Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees, and prohibit discrimination and harassment of any type, without regard to race, sex, pregnancy, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.
Mandatory Notices
U.S. Export Controls Disclaimer: In accordance with the U.S. Export Administration Regulations (15 CFR §743.13(b)), some roles at Intuitive Surgical may be subject to U.S. export controls for prospective employees who are nationals from countries currently on embargo or sanctions status.
Certain information you provide as part of the application will be used for purposes of determining whether Intuitive Surgical will need to (i) obtain an export license from the U.S. Government on your behalf (note: the government’s licensing process can take 3 to 6+ months) or (ii) implement a Technology Control Plan (“TCP”) (note: typically adds 2 weeks to the hiring process).
For any Intuitive role subject to export controls, final offers are contingent upon obtaining an approved export license and/or an executed TCP prior to the prospective employee’s start date, which may or may not be flexible, and within a timeframe that does not unreasonably impede the hiring need. If applicable, candidates will be notified and instructed on any requirements for these purposes.
We will consider for employment qualified applicants with arrest and conviction records in accordance with fair chance laws.
Preference will be given to qualified candidates who do not reside, or plan to reside, in Alabama, Arkansas, Delaware, Florida, Indiana, Iowa, Louisiana, Maryland, Mississippi, Missouri, Oklahoma, Pennsylvania, South Carolina, or Tennessee.
This position may be filled at a different job level than listed here depending on
business need and/or on the selected candidate’s experience, knowledge and skills.
Compensation will be based primarily on the job level at which the role is filled and the
candidate’s qualifications, consistent with applicable law.
We provide market-competitive compensation packages, inclusive of base pay, incentives, benefits, and equity. It would not be typical for someone to be hired at the top end of range for the role, as actual pay will be determined based on several factors, including experience, skills, and qualifications. The target compensation ranges are listed.
Base Compensation Range Region 1: $178,800 USD - $257,200 USD
Base Compensation Range Region 2: $152,000 USD - $218,600 USD
Shift: Day
Workplace Type: Onsite - This job is fully onsite.
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Find JobsSenior Level Design Verification Job Market
Who's Hiring
- Apple56
- NVIDIA14
- Google12
- Micron Idaho Semiconductor Manufacturing (Triton)9

- Tenstorrent6

Top Industries Hiring
- Electronics & Hardware138
- Technology & Software57
- Artificial Intelligence16
- Telecommunications10
- Automotive7
Senior Level Design Verification Jobs: Frequently Asked Questions
How do I get a senior level design verification job?
Employers at this level want engineers who have owned verification plans end to end, not just executed tasks assigned by others. Demonstrated expertise in formal verification, UVM-based testbench architecture, or coverage closure on complex SoCs gives candidates a strong edge. Leadership signals matter too, such as mentoring junior engineers, driving methodology decisions, and presenting sign-off results to design and program teams.
Which companies hire senior level design verifications?
Companies hiring senior level design verifications right now include Apple, NVIDIA, and Google, based on current listings on Migrate Mate as of July 2026. Hiring at this level tends to concentrate in semiconductor companies, EDA vendors, and large systems firms that run multi-year chip development programs requiring deep verification ownership.
Are there remote senior level design verification jobs?
Yes, though on-site and hybrid arrangements remain common given lab access and team collaboration demands. About 23% of senior level design verification openings are remote or hybrid as of July 2026, with fully remote roles more common at companies using distributed design teams or cloud-based simulation infrastructure.
What makes a design verification role senior level?
Senior level design verification roles are defined by ownership and scope rather than task execution. At this level, engineers lead the verification planning for a block, subsystem, or full chip, make methodology calls, and are accountable for coverage closure and sign-off readiness. Mentoring less experienced engineers and collaborating directly with design leads and program managers are also standard expectations.
Which industries hire the most senior level design verifications?
Senior Level design verification roles concentrate in Electronics & Hardware, Technology & Software, and Artificial Intelligence, based on current listings on Migrate Mate as of July 2026. These sectors drive hiring at this level because they run high-complexity silicon programs where verification depth and ownership directly affect product risk, tape-out schedules, and long-term platform reliability.