Senior Level Senior Physical Design Engineer Jobs
Senior level senior physical design engineer jobs place experienced engineers at the forefront of chip architecture decisions, owning full physical implementation flows, driving design closure, and guiding junior engineers through complex tapeout challenges. Openings concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, with a mix of on-site, hybrid, and remote positions available, and employers like Apple, Intel, and Micron Technology hiring at this level now.
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Showing 5 of 108+ Senior Level Senior Physical Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
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Who's Hiring
- Apple33
- Intel11
- Micron Technology6
- Qualcomm5
- Tenstorrent5
Top Industries Hiring
- Electronics & Hardware78
- Technology & Software18
- Consulting & Professional Services11
- Telecommunications4
- Artificial Intelligence4
Senior Level Senior Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level senior physical design engineer job?
Employers at this level look for engineers who have owned physical implementation from floorplan through signoff on multiple production tapeouts, not just contributed to one. Demonstrating expertise in timing closure, power delivery, and design rule compliance on advanced process nodes is essential. Candidates who can show they have mentored others and made architectural trade-off decisions independently stand out most in competitive searches.
Which companies hire senior level senior physical design engineers?
Companies hiring senior level senior physical design engineers right now include Apple, Intel, and Micron Technology, based on current listings on Migrate Mate as of July 2026. Hiring at this level tends to come from semiconductor firms, fabless chip designers, and large technology companies running in-house silicon programs who need engineers capable of leading critical workstreams end to end.
Are there remote senior level senior physical design engineer jobs?
Yes, though on-site and hybrid roles remain common given the tool access and collaboration these positions require. About 25% of senior level senior physical design engineer openings are remote or hybrid as of July 2026, so flexibility exists depending on employer and project stage. Searching by work setting on Migrate Mate lets you filter to arrangements that fit your situation.
What makes a senior physical design engineer role senior level?
Senior level roles are defined by ownership and scope rather than task execution. A senior physical design engineer is expected to drive an entire implementation block or subsystem independently, make architectural and methodology decisions, resolve complex physical verification failures without escalation, and actively mentor mid-level engineers. These roles carry direct accountability for tapeout readiness and are differentiated from mid-level positions by that depth of autonomous technical leadership.
Which industries hire the most senior level senior physical design engineers?
Senior level senior physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, based on current listings on Migrate Mate as of July 2026. These sectors drive hiring at this level because they are investing heavily in custom silicon development, where experienced engineers who can own physical design from concept through production sign-off are in consistent demand.