SoC Design Verification Engineer Jobs
SoC Design Verification Engineer jobs are open across semiconductor, consumer electronics, aerospace, and automotive industries, from new-grad to principal and staff levels, with specializations in functional verification, UVM testbench development, and formal verification. See the openings below and apply to the ones that match your experience.
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Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure every implementation step preserves functional intent and power intent. This is a hands-on role with opportunities to own block and full-chip formal signoff and shape formal methodology across multiple product generations.
Key Responsibilities
- Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist (post-synthesis, post-DFT insertion, post-CTS, post-route), and ECO netlists.
- Develop and maintain robust equivalence setups, including handling of retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
- Debug and resolve non-equivalence and abort points efficiently, partnering with RTL, synthesis, DFT, and physical design teams to root-cause issues and converge designs to clean signoff.
- Perform static low-power verification (e.g., Conformal Low Power, VC LP) against UPF power intent, covering isolation, level shifting, retention, power switches, and always-on connectivity through implementation.
- Drive functional ECO generation and implementation using formal ECO tools (e.g., Conformal ECO, Formality ECO), minimizing patch size and physical impact late in the design cycle.
- Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required by signoff criteria.
- Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal verification status in tapeout readiness reviews.
- Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell to improve runtime, capacity, and debug productivity.
- Collaborate with EDA vendors to resolve tool issues, evaluate new capabilities, and adopt best-in-class methodology across product generations.
- Develop agentic AI flows based on latest LLM and Gen-AI capabilities.
Required Qualifications
- Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
- Proficiency with industry formal verification tools (e.g., Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa or equivalent).
- Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step impacts equivalence.
- Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.
- Working knowledge of power intent (UPF/CPF) and low-power design concepts, including isolation, level shifting, retention, and power gating.
- Familiarity with DFT structures (scan, compression, MBIST, JTAG) and their treatment in formal verification.
- Good understanding of Verilog/SystemVerilog and gate-level netlists, and ability to read and reason about RTL and synthesized logic.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Strong scripting/automation skills using Python, TCL, Perl, and/or shell.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
Preferred Qualifications
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Experience with functional ECO generation and implementation on large hierarchical designs.
- Exposure to property-based formal verification (SVA, formal apps) or netlist-level CDC/RDC signoff.
- Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 7 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$124,000.00 - $254,000.00 a yearAdditional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure every implementation step preserves functional intent and power intent. This is a hands-on role with opportunities to own block and full-chip formal signoff and shape formal methodology across multiple product generations.
Key Responsibilities
- Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist (post-synthesis, post-DFT insertion, post-CTS, post-route), and ECO netlists.
- Develop and maintain robust equivalence setups, including handling of retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
- Debug and resolve non-equivalence and abort points efficiently, partnering with RTL, synthesis, DFT, and physical design teams to root-cause issues and converge designs to clean signoff.
- Perform static low-power verification (e.g., Conformal Low Power, VC LP) against UPF power intent, covering isolation, level shifting, retention, power switches, and always-on connectivity through implementation.
- Drive functional ECO generation and implementation using formal ECO tools (e.g., Conformal ECO, Formality ECO), minimizing patch size and physical impact late in the design cycle.
- Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required by signoff criteria.
- Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal verification status in tapeout readiness reviews.
- Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell to improve runtime, capacity, and debug productivity.
- Collaborate with EDA vendors to resolve tool issues, evaluate new capabilities, and adopt best-in-class methodology across product generations.
- Develop agentic AI flows based on latest LLM and Gen-AI capabilities.
Required Qualifications
- Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
- Proficiency with industry formal verification tools (e.g., Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa or equivalent).
- Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step impacts equivalence.
- Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.
- Working knowledge of power intent (UPF/CPF) and low-power design concepts, including isolation, level shifting, retention, and power gating.
- Familiarity with DFT structures (scan, compression, MBIST, JTAG) and their treatment in formal verification.
- Good understanding of Verilog/SystemVerilog and gate-level netlists, and ability to read and reason about RTL and synthesized logic.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Strong scripting/automation skills using Python, TCL, Perl, and/or shell.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
Preferred Qualifications
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Experience with functional ECO generation and implementation on large hierarchical designs.
- Exposure to property-based formal verification (SVA, formal apps) or netlist-level CDC/RDC signoff.
- Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 7 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$124,000.00 - $254,000.00 a yearAdditional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
See All 36 SoC Design Verification Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find JobsSoC Design Verification Engineer Job Market
Who's Hiring
- Apple19
- Qualcomm4
- TikTok2
- Velaura2V
- Ampere Computing2
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
- Telecommunications
- Distribution & Wholesale
What Employers Look For
The qualifications that appear most often in SoC design verification engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM methodology for testbench development
- Experience with industry-standard simulation tools such as VCS, Xcelium, or Questa
- Familiarity with functional coverage, assertion-based verification, and coverage closure
- Knowledge of digital design fundamentals including RTL coding and synthesis flows
- Experience debugging complex SoC designs across multiple clock domains and interfaces
Tips for Your SoC Design Verification Engineer Job Search
Tailor your resume to verification depth
Hiring managers scan for specific verification methodologies before reading anything else. Call out your UVM experience, coverage closure results, and the size of the designs you verified in gate count or complexity, not just the company name or years.
Highlight formal verification separately from simulation
Many soc design verification engineer postings treat formal and simulation as distinct skill sets. If you've used tools like JasperGold or Questa Formal, give that a dedicated resume line so it doesn't get buried under your general testbench work.
Apply early to roles that fit
Migrate Mate lists soc design verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by design node and domain
A role verifying a 3nm mobile SoC requires different expertise than one covering an automotive ASIC at 28nm. When searching, refine by industry and read the job description for the target process node so you're not applying to mismatched roles.
Prepare a coverage closure walkthrough for interviews
Interviewers at semiconductor companies almost always ask how you drove coverage from initial runs to closure. Prepare a concrete example with the starting coverage percentage, the gap analysis method you used, and how long closure took.
Negotiate start date around tapeout schedules
Chip teams hire with tapeout milestones in mind. If an offer comes close to a known tapeout window, asking about the project phase upfront lets you negotiate a start date that doesn't drop you into the highest-pressure week of the cycle.
SoC Design Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most soc design verification engineers?
The companies hiring the most soc design verification engineers right now include Apple, Qualcomm, and TikTok, with the largest share of openings in California, Texas, and Oregon, based on current listings on Migrate Mate as of November 2026. Semiconductor fabless companies and large integrated device manufacturers consistently post the highest volumes of these roles.
How many soc design verification engineer jobs are remote?
About 25% of soc design verification engineer openings are fully remote or hybrid as of November 2026, reflecting the hands-on lab and EDA tool infrastructure many teams require on-site. Roles focused on software-driven simulation and test planning tend to offer the most remote flexibility compared to positions tied to emulation hardware or lab bring-up work.
How do you become a soc design verification engineer?
Start with a degree in electrical engineering, computer engineering, or computer science with coursework in digital design and computer architecture. Build hands-on skills in SystemVerilog and UVM by working through open-source verification projects or academic labs. Internships at semiconductor companies provide real SoC exposure. Entry-level roles often begin with block-level verification before moving to full-chip integration work.
How do you get hired as a soc design verification engineer with little experience?
Focus on demonstrating testbench development skills through personal or academic projects you can walk through in an interview. Contributing to open-source processor verification projects shows initiative. Target positions titled junior verification engineer or verification intern, which explicitly expect less industry exposure. Knowing UVM basics and being able to write a simple directed test from scratch is often enough to pass a first-round technical screen.
What does the soc design verification engineer interview process look like?
Most processes start with a recruiter screen, followed by a technical phone round covering SystemVerilog syntax, UVM architecture, and basic digital design questions. An on-site or virtual loop typically includes a coding exercise where you write a testbench component, a design debug session using waveforms, and a system-design discussion about verifying a small block from scratch. Final rounds often include a hiring manager conversation about project scope and team fit.
Where can I find and apply to soc design verification engineer jobs?
You can find and apply to soc design verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Search for roles that match your verification background and seniority level, then apply directly to each listing that fits.
See All 36 SoC Design Verification Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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