SoC Engineer Jobs
SoC Engineer jobs are open across semiconductor, consumer electronics, aerospace, and automotive industries, at every level from new-grad to principal, with specializations in digital design, mixed-signal integration, and power management. Scan the live roles below and apply to whichever ones fit.
Find SoC Engineer JobsLooking for remote work? View remote SoC engineer jobs →Overview
Open roles295+
Top stateCalifornia
Top employerApple
Top citySan Diego, CA
Work type67% On-site
Top industryElectronics
Showing 5 of 295+ SoC Engineer jobs
HBM SoC Physical Design Engineer
We won't show you this job again
New 15h ago
Micron Technology
HBM SoC Physical Design Engineer
Folsom, California
New 15h ago
SoC Physical Design Formal Verification Engineer, HBM
We won't show you this job again
New 15h ago
Micron Technology
SoC Physical Design Formal Verification Engineer, HBM
Folsom, California
New 15h ago
Principal SoC DFT Engineer, HBM
We won't show you this job again
New 15h ago
Micron Technology
Principal SoC DFT Engineer, HBM
Folsom, California
New 15h ago
SOC Engineer
We won't show you this job again
New 17h ago
J2B GLOBAL LLC
SOC Engineer
San Jose, California
New 17h ago
Embedded Software / Firmware Engineer – Automotive MCU & SoC
We won't show you this job again
New 22h ago
Stellantis
Embedded Software / Firmware Engineer – Automotive MCU & SoC
Auburn Hills, Michigan
New 22h ago
New 15h ago
HBM SoC Physical Design Engineer
Micron Technology·Folsom, California
Job functions:
$146k - $247k/yr
Bachelor's degree in electrical engineering
10,000+ employees
Job Description
Job ID
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
Micron Technology
HBM SoC Physical Design Engineer
Folsom, California
New 15h ago10,000+ employees
Job functions:
$146k - $247k/yr
Bachelor's degree in electrical engineering
Job Description
Job ID
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
SoC Engineer Jobs by Experience Level
See All 295+ SoC Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find SoC Engineer JobsSoC Engineer Job Market
Who's Hiring
- Apple142
- Qualcomm19
- Amazon Web Services12
- NVIDIA8
- AMD7
Top Industries Hiring
- Electronics & Hardware43
- Technology & Software10
- Automotive3
- Telecommunications3
- Medical Devices1
What Employers Look For
The qualifications that appear most often in SoC engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Hands-on experience with RTL design and synthesis using Verilog or SystemVerilog
- Proficiency with industry EDA tools such as Synopsys Design Compiler, Cadence Innovus, or equivalent
- Experience with SoC integration including bus protocols such as AMBA, AXI, or APB
- Familiarity with physical design flows including floorplanning, place-and-route, and timing closure
- Experience with low-power design techniques including clock gating and power domain partitioning
Tips for Your SoC Engineer Job Search
Tailor your resume to tapeout milestones
Hiring managers for soc engineer roles scan for concrete tapeout experience. List the process node, the IP blocks you owned, and whether the chip reached production. Generic RTL experience without that context rarely clears the first screen.
Apply early to roles that fit
Migrate Mate lists soc engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by design methodology
Job postings for soc engineer roles often specify physical design, verification, or firmware integration as the primary focus. Targeting postings that match your deepest skill set, rather than applying broadly, produces better callback rates and more relevant interviews.
Highlight tool fluency beyond the obvious
Most candidates list Synopsys or Cadence. Differentiate yourself by calling out experience with specific flows: formal verification using JasperGold, low-power analysis in Voltus, or timing closure in Tempus. Tool depth signals readiness to contribute on day one.
Prepare for architecture deep-dives in interviews
SoC engineer interviews frequently go beyond RTL coding questions into bus architecture decisions, memory subsystem tradeoffs, and power domain partitioning. Practice explaining design choices you made and the constraints that shaped them, not just what you built.
Negotiate by anchoring to process node and IP complexity
When discussing compensation, frame your experience around the most advanced node you've taped out on and the complexity of IP blocks you've integrated. Teams working at leading-edge nodes and high IP counts consistently value those specifics more than years of experience alone.
SoC Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most soc engineers?
The most active employers for soc engineers right now are Apple, Qualcomm, and Amazon Web Services, and the most openings are in California, Texas, and Oregon, based on current listings on Migrate Mate as of November 2026. Demand is especially concentrated at semiconductor companies developing custom silicon for AI, mobile, and automotive applications.
How many soc engineer jobs are remote?
About 33% of soc engineer openings are fully remote or hybrid as of November 2026, reflecting the hands-on lab and EDA tool access this role often requires. Verification-focused and firmware integration sub-roles tend to offer the most remote flexibility, while physical design and tapeout roles more frequently require on-site presence.
How do you become a soc engineer?
Start with a degree in electrical or computer engineering with coursework in digital logic, computer architecture, and VLSI design. Build RTL design and simulation skills through coursework or personal projects, then pursue internships or entry-level roles focused on RTL verification or digital design. Progress by gaining exposure to full chip integration flows, EDA toolchains, and tapeout cycles across increasingly complex designs.
How do you get hired as a soc engineer with little experience?
Focus on roles titled digital design engineer, RTL verification engineer, or ASIC design engineer, which share core skills with soc engineering and serve as common entry points. Build a portfolio of personal or academic RTL projects, contribute to open-source hardware projects, and target companies with structured new-grad programs in their hardware engineering organizations.
What does the soc engineer interview process look like?
Most soc engineer interviews include a recruiter screen, a technical phone or video round covering RTL design and verification concepts, and an on-site or virtual loop with multiple engineers. On-site rounds typically include a coding or design exercise in Verilog or SystemVerilog, a system architecture discussion, and a behavioral interview. Some companies add a take-home design problem before the final loop.
Where can I find and apply to soc engineer jobs?
You can find and apply to soc engineer jobs on Migrate Mate, which lists current openings from across the United States. Search for roles that match your specialization and experience level, then apply directly to each listing that fits.
See All 295+ SoC Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find SoC Engineer Jobs