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About this opportunity:

Principal CAD RTL Methodology and Design Engineer

Austin, Texas. This is not a remote work opportunity.

Define how Ericsson writes and signs off RTL, from coding rules to lint, CDC and RDC sign off. Combine hands-on RTL design with methodology leadership, software engineering, and practical AI to raise design quality across ASIC and FPGA programs.

Work on ASIC and FPGA programs for Ericsson’s 5G and 6G portfolio at advanced nodes, including Intel 18A and TSMC 3/2nm. Drive measurable gains in RTL quality, IP reuse, and time to a qualified netlist through vendor-agnostic static signoff, reusable RTL frameworks, and AI-assisted design.

We are seeking a hands-on technical leader to own our RTL design methodology and static signoff flows—not simply support existing tools. Roughly half your time is spent on RTL design, so methodology decisions stay grounded in real product work.

You will work across RTL design automation, verification methodology, and OneRun, our front-end flow orchestration platform, partnering with IP and SoC design leads, domain methodology leads, back-end teams, and EDA vendors across Austin, Stockholm, Lund, and India. Own technical direction and qualified methodology; partner with the Silicon CAD Technical Program Manager on integrated delivery and adoption. Project design leads retain RTL signoff approval.

What you will do

• Own RTL design methodology: Define coding guidelines, lint rule sets, waiver policy, and signoff criteria for IP, subsystem, and SoC teams. Govern changes with design leads and mentor engineers in RTL best practices.
• Lead lint, CDC, and RDC signoff: Architect structural, formal, and hybrid CDC and RDC flows with progressive goals and hierarchical signoff using abstract models and clock/reset constraints. Keep signoff criteria independent of the tool.
• Build vendor-agnostic flows: Deliver single-command static signoff in OneRun with standard project templates and Jenkins CI quality gates. Qualify rule mapping between vendor tools on clean and dirty RTL before production use.
• Drive RTL reuse and automation: Architect configurable RTL frameworks and standard interfaces for multi-program IP reuse. Set the strategy for our next-generation register generation tool, with generated RTL that is signoff-clean.
• Apply AI to RTL engineering: Use and improve AI tools such as ChipAgents and Kiro for RTL development, documentation, code conversion, and lint and CDC triage. Evaluate against manual baselines; retain engineering review.
• Strengthen the FE–BE handoff: Define RTL quality, SDC, and UPF checks for netlist handoff with synthesis, DFT, and back-end teams. Roll out changes through representative pilots without disrupting active tapeout schedules.

Join our Team

What you will bring

• 10+ years in ASIC/SoC RTL design and front-end methodology, with evidence of production deployment and successful tapeout contributions.
• Deep hands-on expertise in SystemVerilog/Verilog RTL design and microarchitecture for complex IP and SoC blocks, including parameterized and low-power design with UPF.
• Strong experience with Synopsys VC SpyGlass and/or Cadence JasperGold for lint, CDC, and RDC, plus an understanding of synthesis, timing, and DFT dependencies. Specialist depth in one or more signoff domains is valued; expertise in every domain is not required.
• Strong Python and scripting skills, with experience building maintainable automation using Linux, version control, code review, CI, automated tests, and controlled releases.
• Demonstrated ability to set standards that design teams adopt, explain technical trade-offs, and lead through technical credibility across distributed teams.
• A bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field—or equivalent practical experience.

Own the engineering behind how RTL is written and signed off—not just a step within it. Shape methodology while staying hands-on in design, work directly with IP and SoC teams and EDA vendors, and turn new methodology and AI ideas into production capabilities. Your impact will be measured in cleaner RTL, faster integration, and signoff flows that designers trust across programs.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.

Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.

If you need assistance or to request an accommodation due to a disability, please contact Ericsson at hr.direct.americas@ericsson.com.

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Primary country and city: USA || Austin, Texas

Job details: Developer

Primary Recruiter: Jim Everett

Compensation and Benefits at Ericsson

At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay

The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.

Short-Term Variable Compensation Plan: Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit’s objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.

Your Health

Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security

We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.

Your Time

Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits

Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.