Senior Level ASIC Design Engineer Jobs
Senior level asic design engineer jobs place experienced engineers at the center of architectural decisions, IP ownership, and the cross-functional teams that bring complex silicon from concept to tape-out. Roles are concentrated across Electronics & Hardware, Technology & Software, and Artificial Intelligence, with 24% offering remote or hybrid work, and employers like Apple, NVIDIA, and Google hiring at this level now.
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Showing 5 of 99+ Senior Level ASIC Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
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Find JobsSenior Level ASIC Design Engineer Job Market
Who's Hiring
- Apple15
- NVIDIA11
- Google6
- Broadcom5
- Synopsys5
Top Industries Hiring
- Electronics & Hardware47
- Technology & Software35
- Artificial Intelligence8
- Telecommunications7
- Law & Legal Services6
Senior Level ASIC Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level asic design engineer job?
Senior level roles go to engineers who can demonstrate ownership of complete design blocks or subsystems, not just task execution. Employers look for candidates who have driven RTL design from spec through signoff, led timing closure on complex hierarchies, and mentored junior engineers through the process. A portfolio of tape-outs, documented design decisions, and cross-functional collaboration experience gives candidates the clearest edge at this stage.
Which companies hire senior level asic design engineers?
Companies hiring senior level asic design engineers right now include Apple, NVIDIA, and Google, based on current listings on Migrate Mate as of July 2026. Hiring at this level is concentrated among semiconductor manufacturers, fabless chip design houses, and large technology companies that develop custom silicon for consumer, automotive, or data center applications.
Are there remote senior level asic design engineer jobs?
Yes, though fully remote roles are less common here than in software engineering given the lab and tool infrastructure involved. About 24% of senior level asic design engineer openings are remote or hybrid as of July 2026, with hybrid arrangements being the more typical setup, allowing engineers to access EDA tools and collaborate on physical design reviews on-site part of the time.
What makes a asic design engineer role senior level?
A senior level asic design engineer role is defined by scope, ownership, and influence rather than task volume. Senior engineers own entire design blocks or subsystems, set micro-architectural direction, resolve complex timing and power trade-offs independently, and review and guide the work of less experienced engineers. They interface directly with architecture, verification, and physical design teams, and their decisions carry direct consequences for tapeout schedules and silicon quality.
Which industries hire the most senior level asic design engineers?
Senior level asic design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Artificial Intelligence, based on current listings on Migrate Mate as of July 2026. These sectors drive demand because they rely on proprietary silicon for performance, power efficiency, or competitive differentiation, making experienced design engineers essential to product roadmaps rather than optional headcount.