ASIC Design Verification Engineer Jobs
ASIC Design Verification Engineer jobs are open across semiconductor, defense, consumer electronics, and automotive industries, covering specializations in functional verification, formal verification, and UVM methodology, from junior to principal and staff levels. Find a role that fits below and apply directly.
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K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
ASIC Design Verification Engineer Jobs by Experience Level
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Find JobsASIC Design Verification Engineer Job Market
Who's Hiring
Top Industries Hiring
- Technology & Software
- Electronics & Hardware
- Telecommunications
- Staffing & Recruiting
- Artificial Intelligence
What Employers Look For
The qualifications that appear most often in ASIC design verification engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM-based testbench development
- Experience with industry EDA simulation tools such as VCS, Questa, or Xcelium
- Hands-on knowledge of functional coverage, code coverage closure, and assertion writing
- Familiarity with formal verification tools such as JasperGold or VC Formal
- Ability to read and interpret RTL design specifications and microarchitecture documents
Tips for Your ASIC Design Verification Engineer Job Search
Tailor your resume to verification depth
Hiring managers scan for specific verification languages and methodologies, so list your UVM, SystemVerilog, and assertion-based verification experience with concrete project context. Naming the design complexity and block size you worked on sets you apart from generalist applicants.
Highlight coverage closure experience explicitly
Many candidates mention simulation but skip coverage closure, which is where most team gaps exist. Call out your code coverage, functional coverage, and any formal property checking work in a dedicated skills section so reviewers find it without guessing.
Apply early to roles that fit
Migrate Mate lists asic design verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target postings by design node and tool stack
Job titles for this role vary widely between companies, so search by tool names like VCS, Questa, Xcelium, or Cadence JasperGold alongside the role title. Filtering by EDA tool narrows results to teams whose environment matches your hands-on experience.
Prepare a verification plan walkthrough for interviews
Most technical screens for this role include a whiteboard or discussion exercise where you build a verification plan from a spec. Practice walking through stimulus generation, checking, and coverage goals for a small but complete block before your first on-site.
Negotiate around project scope and design access
Compensation is one part of the offer, but early access to RTL, the size of the block you own, and tool licensing directly affect your growth speed. Ask specifically about those during offer discussions so you understand the working conditions alongside the pay.
ASIC Design Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most asic design verification engineers?
Meta, NVIDIA, and Google are hiring the most asic design verification engineers right now, with openings concentrated in California, Texas, and Colorado, based on current listings on Migrate Mate as of November 2026. Demand is strongest at fabless semiconductor companies and large consumer electronics firms building custom silicon.
How many asic design verification engineer jobs are remote?
About 62% of asic design verification engineer openings are fully remote or hybrid as of November 2026, reflecting the hands-on EDA tool access that most verification roles require. Pre-silicon verification work that relies on cloud-based simulation environments tends to offer the most remote flexibility compared to roles tied to lab hardware or emulation platforms.
How do you become a asic design verification engineer?
Start with a degree in electrical engineering, computer engineering, or a closely related field, with coursework in digital logic design and computer architecture. Build SystemVerilog and UVM skills through academic projects or personal testbench work on open-source RTL designs. Internships at semiconductor companies provide the practical EDA tool exposure that most entry-level job postings expect before your first full-time hire.
How do you get hired as a asic design verification engineer with little experience?
Contribute to an open-source chip project using a public RTL repository and write a UVM testbench you can walk through in an interview. Coursework projects that demonstrate coverage closure and bug hunting in simulation carry real weight when you lack industry experience. Entry-level postings often look for strong scripting skills in Python or Perl alongside verification fundamentals, so showing those in your resume compensates for a shorter work history.
What does the asic design verification engineer interview process look like?
Most processes start with a recruiter screen followed by a technical phone interview covering SystemVerilog syntax, UVM architecture, and coverage concepts. An on-site or virtual loop typically includes a verification planning exercise, a debugging session where you trace through a waveform or log to find a bug, and a behavioral round with the team lead. Some companies add a short take-home coding assignment involving a testbench component before the on-site stage.
Where can I find and apply to asic design verification engineer jobs?
You can find and apply to asic design verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Search the listings to find roles that match your skills, experience level, and preferred location, then apply directly to each opening that fits.
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