Mid Level Asic Verification Engineer Jobs
Mid level asic verification engineer jobs go to engineers ready to own verification plans end to end, lead coverage closure on complex blocks, and guide junior engineers with limited oversight. Openings are concentrated across on-site and hybrid settings in Technology & Software, Electronics & Hardware, and Artificial Intelligence, with Google, NVIDIA, and Waymo hiring at this level now.
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INTRODUCTION
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to verify the digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with formal and design verification.
- Experience with SystemVerilog or Verilog.
- Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
PREFERRED QUALIFICATIONS
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
- Experience with scripting languages.
- Excellent communication and collaboration skills.
Responsibilities
- Plan the formal verification strategy, create the properties and constraints for the digital design blocks.
- Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
- Resolve difficult to verify properties.
- Contribute improvements to methodologies to enhance formal verification results.
- Architect and implement reusable formal verification components.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
INTRODUCTION
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to verify the digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with formal and design verification.
- Experience with SystemVerilog or Verilog.
- Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
PREFERRED QUALIFICATIONS
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
- Experience with scripting languages.
- Excellent communication and collaboration skills.
Responsibilities
- Plan the formal verification strategy, create the properties and constraints for the digital design blocks.
- Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
- Resolve difficult to verify properties.
- Contribute improvements to methodologies to enhance formal verification results.
- Architect and implement reusable formal verification components.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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Mid Level Asic Verification Engineer Jobs: Frequently Asked Questions
How do I get a mid level asic verification engineer job?
Position your experience around ownership, not just execution. Highlight blocks or subsystems you led verification on independently, methodologies you selected, and coverage goals you defined rather than inherited. Demonstrable fluency in SystemVerilog and UVM, combined with experience closing bugs across RTL, gate, or post-silicon stages, signals mid level readiness to most hiring teams. Tailor each application to the specific verification environment the role uses.
Which companies hire mid level asic verification engineers?
Companies hiring mid level asic verification engineers right now include Google, NVIDIA, and Waymo, based on current listings on Migrate Mate as of August 2026. Hiring at this level covers semiconductor design houses, fabless chip startups, and large technology companies building custom silicon for compute, networking, or mobile applications.
Are there remote mid level asic verification engineer jobs?
Yes, though on-site and hybrid arrangements are more common in this discipline given the lab and simulation infrastructure many teams rely on. About 14% of mid level asic verification engineer openings are remote or hybrid as of August 2026, so filtering by work setting when you search will help you focus on openings that match your situation.
How do I move up to a mid level asic verification engineer role?
Growing into a mid level asic verification engineer role comes from progressively owning larger scopes of work over your first few years. Building depth in UVM testbench architecture, taking responsibility for coverage plans rather than just writing individual tests, and demonstrating that your verification catches real bugs before tape-out all signal readiness. Documenting measurable contributions, such as coverage closure rates or regression reduction, strengthens the case for promotion or a lateral move at a higher level.
Which industries hire the most mid level asic verification engineers?
Mid Level asic verification engineer roles concentrate in Technology & Software, Electronics & Hardware, and Artificial Intelligence, based on current listings on Migrate Mate as of August 2026. Those sectors drive hiring at this level because they are actively designing or integrating custom silicon for high-performance computing, communications, and consumer devices, where rigorous pre-silicon verification is critical to product success.