Mid Level Asic Verification Engineer Jobs
Mid level asic verification engineer jobs go to engineers ready to own verification plans end to end, lead coverage closure on complex blocks, and guide junior engineers with limited oversight. Openings are concentrated across on-site and hybrid settings in Technology & Software, Artificial Intelligence, and Electronics & Hardware, with Google, NVIDIA, and Waymo hiring at this level now.
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Showing 5 of 19+ Mid Level Asic Verification Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with design verification.
- Experience with SystemVerilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.
- Experience in the full verification life-cycle from test planning to coverage closure.
- Experience with 2 or more SoC projects/cycles.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with design verification.
- Experience with SystemVerilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.
- Experience in the full verification life-cycle from test planning to coverage closure.
- Experience with 2 or more SoC projects/cycles.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
See All 19 Mid Level Asic Verification Engineer Jobs
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Find JobsMid Level Asic Verification Engineer Job Market
Who's Hiring
- Google6
- NVIDIA5
- Waymo2
- MaxLinear2
- Broadcom1
Top Industries Hiring
- Technology & Software12
- Artificial Intelligence6
- Electronics & Hardware5
- Law & Legal Services2
Mid Level Asic Verification Engineer Jobs: Frequently Asked Questions
How do I get a mid level asic verification engineer job?
Position your experience around ownership, not just execution. Highlight blocks or subsystems you led verification on independently, methodologies you selected, and coverage goals you defined rather than inherited. Demonstrable fluency in SystemVerilog and UVM, combined with experience closing bugs across RTL, gate, or post-silicon stages, signals mid level readiness to most hiring teams. Tailor each application to the specific verification environment the role uses.
Which companies hire mid level asic verification engineers?
Companies hiring mid level asic verification engineers right now include Google, NVIDIA, and Waymo, based on current listings on Migrate Mate as of July 2026. Hiring at this level covers semiconductor design houses, fabless chip startups, and large technology companies building custom silicon for compute, networking, or mobile applications.
Are there remote mid level asic verification engineer jobs?
Yes, though on-site and hybrid arrangements are more common in this discipline given the lab and simulation infrastructure many teams rely on. About 33% of mid level asic verification engineer openings are remote or hybrid as of July 2026, so filtering by work setting when you search will help you focus on openings that match your situation.
How do I move up to a mid level asic verification engineer role?
Growing into a mid level asic verification engineer role comes from progressively owning larger scopes of work over your first few years. Building depth in UVM testbench architecture, taking responsibility for coverage plans rather than just writing individual tests, and demonstrating that your verification catches real bugs before tape-out all signal readiness. Documenting measurable contributions, such as coverage closure rates or regression reduction, strengthens the case for promotion or a lateral move at a higher level.
Which industries hire the most mid level asic verification engineers?
Mid Level asic verification engineer roles concentrate in Technology & Software, Artificial Intelligence, and Electronics & Hardware, based on current listings on Migrate Mate as of July 2026. Those sectors drive hiring at this level because they are actively designing or integrating custom silicon for high-performance computing, communications, and consumer devices, where rigorous pre-silicon verification is critical to product success.