Mid Level ASIC Design Engineer Jobs
Mid level asic design engineer jobs go to engineers ready to own blocks or subsystems end to end, make microarchitecture decisions with limited oversight, and mentor junior colleagues on design and verification flows. Openings are distributed across on-site, hybrid, and remote settings in Technology & Software, Electronics & Hardware, and Artificial Intelligence, with employers like NVIDIA, Apple, and Google actively hiring at this level now.
Find JobsOverview
Showing 5 of 73+ Mid Level ASIC Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with design verification.
- Experience with SystemVerilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.
- Experience in the full verification life-cycle from test planning to coverage closure.
- Experience with 2 or more SoC projects/cycles.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with design verification.
- Experience with SystemVerilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.
- Experience in the full verification life-cycle from test planning to coverage closure.
- Experience with 2 or more SoC projects/cycles.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
See All 73 Mid Level ASIC Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find JobsMid Level ASIC Design Engineer Job Market
Who's Hiring
- NVIDIA15
- Apple7
- Google6
- Broadcom5
- Cisco3
Top Industries Hiring
- Technology & Software31
- Electronics & Hardware23
- Artificial Intelligence8
- Law & Legal Services5
- Aerospace & Defense3
Mid Level ASIC Design Engineer Jobs: Frequently Asked Questions
How do I get a mid level asic design engineer job?
Lead with ownership: highlight chips or blocks you took from RTL through tapeout with minimal guidance, and call out any cross-functional decisions you drove independently. Tailor your resume to the specific process node and toolchain listed in the job description, whether that is front-end synthesis, physical design, or DFT. Concrete metrics, such as area reduction or timing closure improvements, carry more weight than job titles alone.
Which companies hire mid level asic design engineers?
Companies hiring mid level asic design engineers right now include NVIDIA, Apple, and Google, based on current listings on Migrate Mate as of July 2026. Hiring at this level comes from a mix of established semiconductor companies, hyperscaler silicon teams building custom compute hardware, and defense contractors developing application-specific processors for specialized systems.
Are there remote mid level asic design engineer jobs?
Yes, though fully remote roles are less common in hardware than in software disciplines due to lab and toolchain access requirements. About 18% of mid level asic design engineer openings are remote or hybrid as of July 2026, with hybrid arrangements being the most prevalent, typically requiring on-site presence for bringup, lab work, or design reviews.
How do I move up to a mid level asic design engineer role?
The path from entry level to mid level centers on building depth in a specific design domain, such as RTL design, physical implementation, or verification, while progressively taking on more complex blocks with less supervision. Engineers who advance fastest seek out tapeout experience early, document measurable contributions to each project, and volunteer to mentor interns or new hires, demonstrating the judgment that mid level roles require.
Which industries hire the most mid level asic design engineers?
Mid Level asic design engineer roles concentrate in Technology & Software, Electronics & Hardware, and Artificial Intelligence, based on current listings on Migrate Mate as of July 2026. Those sectors drive demand because they require custom silicon to meet performance, power, or latency targets that off-the-shelf chips cannot achieve, making experienced asic designers a sustained hiring priority.