Senior Level Design Verification Engineer Jobs
Senior level design verification engineer jobs place experienced engineers in ownership roles, leading verification strategy, defining coverage methodology, and driving sign-off decisions across complex SoC and ASIC projects. Openings are concentrated across on-site, hybrid, and remote settings in Electronics & Hardware, Technology & Software, and Artificial Intelligence, with employers like Apple, Google, and Tenstorrent hiring at this level now.
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Would you like to join Apple’s growing wireless silicon development team? Our wireless SoC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering.
Description
In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.
Responsibilities
- Work closely with the system and design teams to review and understand the MAC subsystem microarchitecture, and create verification plan from specification, review and refine to achieve coverage targets.
- Build block/subsystem level test benches, create UVM libraries, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind.
- Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
- Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
- Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
- Support MAC subsystem validation using Palladium and/or FPGA.
- Work with team members to improve DV methodology and flow.
Minimum Qualifications
- BS and a minimum of 10 years relevant industry experience.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
- Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine.
Preferred Qualifications
- 7+ years of verification experience of wireless/wired communication block/subsystem.
- Verification experience of wireless/wired communication block/subsystem.
- Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
- Proficient in shell and Python scripting, Perl scripting.
- Experience of using AI technologies in data mining/analysis.
- Experience of Palladium/FPGA validation.
- Should be a team player with excellent communication skills, self-motivated and well organized.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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Senior Level Design Verification Engineer Jobs: Frequently Asked Questions
How do I get a senior level design verification engineer job?
Employers hiring at the senior level expect you to own verification plans end to end, not just execute tasks. Demonstrating depth in functional coverage closure, assertion-based verification, and UVM methodology is table stakes. What separates candidates at this stage is the ability to define the verification strategy for a block or subsystem, mentor junior engineers, and communicate sign-off readiness to design and program leadership.
Which companies hire senior level design verification engineers?
Companies hiring senior level design verification engineers right now include Apple, Google, and Tenstorrent, based on current listings on Migrate Mate as of November 2026. Hiring at this level comes primarily from semiconductor manufacturers, fabless chip companies, and large technology firms with dedicated silicon design teams.
Are there remote senior level design verification engineer jobs?
Yes, though availability varies by employer and project sensitivity. About 50% of senior level design verification engineer openings are remote or hybrid as of November 2026, reflecting growing flexibility in the field. Fully remote roles tend to appear more often at companies with distributed verification teams, while on-site positions remain common where lab access or proprietary tool environments are required.
What makes a design verification engineer role senior level?
Senior level roles are defined by ownership and scope rather than task completion. A senior design verification engineer is expected to author the verification plan, drive coverage closure decisions, identify gaps in the test environment, and often lead or mentor a small team. They interface directly with design leads and program managers, and their sign-off carries real accountability for tape-out quality.
Which industries hire the most senior level design verification engineers?
Senior level design verification engineer roles concentrate in Electronics & Hardware, Technology & Software, and Artificial Intelligence, based on current listings on Migrate Mate as of November 2026. These sectors drive demand because they develop complex, high-reliability silicon where rigorous pre-silicon verification is essential to meet performance targets and avoid costly re-spins.