Senior Level Asic Verification Engineer Jobs
Senior level asic verification engineer jobs place experienced engineers in ownership of verification architecture, methodology decisions, and the complex SoC and IP validation programs that define a chip's quality. Openings are concentrated in Electronics & Hardware, Telecommunications, and Technology & Software, with a mix of on-site, hybrid, and remote positions, and employers like Nokia, Axiado, and Google hiring at this level now.
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Senior ASIC Design Verification Engineer - Slingshot
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
About the Team and the Project
Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems. As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own significant verification scope, set technical direction for a block or subsystem, and help shape how our team applies emerging agentic AI workflows to solve complex engineering problems.
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.
Responsibilities
- Follow and help define the team's design verification methodology.
- Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
- Plan and implement block and integration level scoreboards and checkers to verify functional behavior.
- Write and analyze functional coverage, providing input to block level milestones.
- Triage regression failures and identify logic bugs, while driving bug closure.
- Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
- Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.
- Participate in and provide input on the process for selection of future technical leaders.
- Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.
Education and Experience Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
- 10+ years of experience in VLSI design, verification, or implementation.
Knowledge and Skills
- Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.
- Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
- Expert level analytical and problem solving skills.
- Ability to excel in a distributed team environment.
- Executive level written and verbal communication skills; mastery in English.
Preferred Skills
- Experience verifying high-speed networking, switching, or NIC ASICs.
- Experience with agentic AI coding tools and workflows applied to verification.
- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
- Experience working as part of a geographically distributed team.
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Job:
Engineering
Job Level:
TCP_04
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 147,000 - 279,000 in Colorado // 140,000 - 321,000 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered.
Information about employee benefits offered in the US can be found at myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is February 1 2027; this timeline is provided for transparency and internal planning purposes.
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.
Senior ASIC Design Verification Engineer - Slingshot
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
About the Team and the Project
Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems. As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own significant verification scope, set technical direction for a block or subsystem, and help shape how our team applies emerging agentic AI workflows to solve complex engineering problems.
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.
Responsibilities
- Follow and help define the team's design verification methodology.
- Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
- Plan and implement block and integration level scoreboards and checkers to verify functional behavior.
- Write and analyze functional coverage, providing input to block level milestones.
- Triage regression failures and identify logic bugs, while driving bug closure.
- Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
- Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.
- Participate in and provide input on the process for selection of future technical leaders.
- Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.
Education and Experience Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
- 10+ years of experience in VLSI design, verification, or implementation.
Knowledge and Skills
- Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.
- Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
- Expert level analytical and problem solving skills.
- Ability to excel in a distributed team environment.
- Executive level written and verbal communication skills; mastery in English.
Preferred Skills
- Experience verifying high-speed networking, switching, or NIC ASICs.
- Experience with agentic AI coding tools and workflows applied to verification.
- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
- Experience working as part of a geographically distributed team.
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Job:
Engineering
Job Level:
TCP_04
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 147,000 - 279,000 in Colorado // 140,000 - 321,000 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered.
Information about employee benefits offered in the US can be found at myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is February 1 2027; this timeline is provided for transparency and internal planning purposes.
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.
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Senior Level Asic Verification Engineer Jobs: Frequently Asked Questions
How do I get a senior level asic verification engineer job?
Employers at this level look for engineers who can own a verification plan end to end, not just execute tasks. Demonstrating expertise in UVM-based testbench architecture, coverage closure, and formal verification tools positions you well. Equally important is showing you have mentored junior engineers, driven methodology improvements, and delivered sign-off on complex blocks or full-chip projects with minimal oversight.
Which companies hire senior level asic verification engineers?
Companies hiring senior level asic verification engineers right now include Nokia, Axiado, and Google, based on current listings on Migrate Mate as of November 2026. Hiring at this level is driven by semiconductor design houses, hyperscaler companies building custom silicon, and defense or aerospace contractors with high-reliability chip programs.
Are there remote senior level asic verification engineer jobs?
Yes, though remote availability varies by employer and project sensitivity. About 40% of senior level asic verification engineer openings are remote or hybrid as of November 2026, making it a realistic option at this stage. Senior engineers with strong asynchronous communication skills and a proven record of independent delivery tend to be the strongest candidates for those flexible arrangements.
What makes a asic verification engineer role senior level?
Senior level asic verification engineer roles are defined by scope, ownership, and influence rather than task execution. At this level, you are expected to define the verification strategy for a block or subsystem, select and drive methodology, review and guide the work of less experienced engineers, and make technical trade-off decisions that affect tape-out timelines. Cross-functional collaboration with design, DFT, and physical implementation teams is a regular part of the role.
Which industries hire the most senior level asic verification engineers?
Senior Level asic verification engineer roles concentrate in Electronics & Hardware, Telecommunications, and Technology & Software, based on current listings on Migrate Mate as of November 2026. These sectors drive demand because they invest heavily in proprietary silicon development, where rigorous pre-silicon verification directly reduces costly respin risk and accelerates time to market.