Design Verification Jobs in Oregon
Design Verification jobs in Oregon are concentrated in the state's robust semiconductor and electronics manufacturing sectors, with demand at every level from entry-level verification engineers to senior architects. Hillsboro, Portland, and Beaverton anchor most of the hiring, home to established employers such as Intel, Tektronix, and Lattice Semiconductor. The most consistent openings are in RTL simulation, functional verification, and UVM-based testbench development. See the openings below and apply to the ones that match your experience.
Find Design Verification JobsOverview
Showing 5 of 10+ Design Verification jobs
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
- Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- BS/MS in Electrical or Computer Engineering/Electrical Engineering
- 5+ years of experience in semiconductor chip design/SOC physical design.
- Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
- Multiple SOC Tape-Out experience in the advanced foundry process nodes.
- Understanding of full chip integration, floor planning, IO RDL and bump planning.
- Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
- Understanding of transistor/device basics.
- Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
- Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- BS/MS in Electrical or Computer Engineering/Electrical Engineering
- 5+ years of experience in semiconductor chip design/SOC physical design.
- Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
- Multiple SOC Tape-Out experience in the advanced foundry process nodes.
- Understanding of full chip integration, floor planning, IO RDL and bump planning.
- Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
- Understanding of transistor/device basics.
- Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
See All 10 Design Verification Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Design Verification JobsDesign Verification Jobs by City in Oregon
Where Oregon roles are concentrated, by current openings.
Design Verification Job Market in Oregon
A snapshot from current Oregon openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Technology & Software
- Artificial Intelligence
- Electronics & Hardware
What Oregon Employers Look For
The qualifications that appear most often in design verification jobs across Oregon.
- Bachelor's degree in electrical engineering, computer engineering, or a closely related field
- Hands-on experience with SystemVerilog and Universal Verification Methodology testbench development
- Proficiency with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Mentor Questa
- Demonstrated ability to write and execute directed and constrained-random verification test plans
- Familiarity with coverage-driven verification methodologies and functional coverage closure
- Strong debugging skills across RTL simulation, waveform analysis, and assertion-based verification
Design Verification Jobs in Oregon: Frequently Asked Questions
How do you become a design verification in Oregon?
Design verification engineers in Oregon do not require a state-issued license, but employers consistently expect a bachelor's degree in electrical engineering, computer engineering, or computer science as the baseline credential. From there, most candidates build hands-on skills through university coursework in digital design and verification, then pursue roles at Oregon's semiconductor companies. Earning industry-recognized credentials such as the Cadence Certified Professional designation strengthens a candidate's profile for Oregon's competitive semiconductor hiring market.
How much do design verifications make in Oregon?
Design verifications in Oregon earn a median of about $124,400 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $80,600 for the lowest 10% to over $215,210 for the top 10%. Pay rises with experience, specialty, and employer.
Which companies hire design verifications in Oregon?
Oregon design verification roles are posted by Apple, Google, and Microsoft and others right now, based on current listings on Migrate Mate as of November 2026. Oregon's concentration of semiconductor fabrication and EDA-tool development companies means design verification is one of the most consistently posted engineering specialties in the state.
Which Oregon cities have the most design verification jobs?
Beaverton, Portland, and Hillsboro have the most design verification openings in Oregon. Hillsboro and Beaverton dominate because Intel's large campus complex and a cluster of semiconductor IP companies are based there, while Portland draws openings from Tektronix, Lattice Semiconductor, and a growing number of fabless chip startups operating out of the metro core.
Are there remote design verification jobs in Oregon?
Yes, but they're less common than in purely software-focused fields because design verification often requires access to licensed EDA tools and lab hardware tied to a physical site. About 50% of design verification openings tied to Oregon are remote or hybrid as of November 2026, and those tend to cluster around test-plan writing, coverage analysis, and regression management rather than hands-on bring-up work.
How can I get hired as a design verification in Oregon with little or no experience?
The most realistic entry path is a new-graduate engineering role at one of Oregon's major semiconductor employers, where structured onboarding into verification teams is common. Intel's university talent programs and Lattice Semiconductor's new-grad engineering tracks in Hillsboro and Portland are practical starting points. Candidates coming from adjacent roles such as FPGA design, software QA, or embedded systems testing can position those skills as directly transferable. A portfolio of open-source UVM testbench projects or a Cadence or Synopsys academic certification gives applicants without professional experience a concrete edge in Oregon interviews.
Where can I find and apply to design verification jobs in Oregon?
You can find and apply to design verification jobs in Oregon on Migrate Mate, which lists current Oregon openings across Hillsboro, Portland, Beaverton, and other locations in the state. Search the listings, identify the roles that fit your background and experience level, and apply directly to the ones that match.
See All 10 Design Verification Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Design Verification Jobs