Design Verification Jobs in Oregon
Design Verification jobs in Oregon are open across Beaverton, Portland, and Hillsboro and other Oregon metros, with employers like Apple, Google, and Ampere Computing hiring at every experience level. Find a role that fits below and apply directly.
Find Design Verification JobsOverview
Showing 5 of 20+ Design Verification jobs
INTRODUCTION
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.
ABOUT THE JOB
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
MINIMUM QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in both Design Verification (UVM/SystemVerilog) and Hardware Emulation.
- Experience reproducing post-silicon lab failures in emulation or simulation environments.
- Experience with industry-standard debug tools (e.g., Synopsys Verdi, Cadence SimVision), with experience using scripting languages (Python, TCL, Bash) to automate debug workflows.
PREFERRED QUALIFICATIONS
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Understanding of CPU/SoC micro-architecture.
- Knowledge of standard high-speed protocols (e.g., PCIe, CXL, AMBA).
- Expertise parsing post-silicon diagnostic artifacts like scan dumps, OS logs, and JTAG traces.
- Excellent communication skills to translate complex technical issues across distinct engineering domains.
Responsibilities
- Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis.
- Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches.
- Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation.
- Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers.
- Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
INTRODUCTION
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.
ABOUT THE JOB
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
MINIMUM QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in both Design Verification (UVM/SystemVerilog) and Hardware Emulation.
- Experience reproducing post-silicon lab failures in emulation or simulation environments.
- Experience with industry-standard debug tools (e.g., Synopsys Verdi, Cadence SimVision), with experience using scripting languages (Python, TCL, Bash) to automate debug workflows.
PREFERRED QUALIFICATIONS
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Understanding of CPU/SoC micro-architecture.
- Knowledge of standard high-speed protocols (e.g., PCIe, CXL, AMBA).
- Expertise parsing post-silicon diagnostic artifacts like scan dumps, OS logs, and JTAG traces.
- Excellent communication skills to translate complex technical issues across distinct engineering domains.
Responsibilities
- Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis.
- Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches.
- Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation.
- Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers.
- Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
See All 20 Design Verification Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Design Verification JobsDesign Verification Jobs by City in Oregon
Where Oregon roles are concentrated, by current openings.
Design Verification Job Market in Oregon
A snapshot from current Oregon openings, updated as new roles post.
Who's Hiring
- Apple12
- Google5
- Ampere Computing2
- Rambus1
Top Industries Hiring
- Electronics & Hardware15
- Artificial Intelligence1
- Technology & Software1
What Oregon Employers Look For
The qualifications that appear most often in design verification jobs across Oregon.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM-based verification environments
- Experience with industry-standard simulators such as Cadence Xcelium, Synopsys VCS, or Mentor Questa
- Hands-on functional coverage closure and assertion-based verification on RTL designs
- Familiarity with formal verification tools such as JasperGold or VC Formal
- Understanding of AMBA protocols including AXI, AHB, or APB for interface-level verification
Design Verification Jobs in Oregon: Frequently Asked Questions
How many design verification jobs are there in Oregon?
There are 20+ design verification openings in Oregon on Migrate Mate as of June 2026, with the most roles in Beaverton, Portland, and Hillsboro. New positions post regularly as employers across Oregon hire.
How much do design verifications make in Oregon?
Design verifications in Oregon earn a median of about $124,400 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $80,600 for the lowest 10% to over $215,210 for the top 10%. Pay rises with experience, specialty, and employer.
Which Oregon cities have the most design verification jobs?
Beaverton, Portland, and Hillsboro have the most design verification openings in Oregon right now, with additional roles spread across smaller metros statewide.
Which companies hire design verifications in Oregon?
Employers hiring design verifications in Oregon include Apple, Google, and Ampere Computing, based on current listings on Migrate Mate as of June 2026.
Are there remote design verification jobs in Oregon?
Yes. About 15% of design verification openings tied to Oregon are remote or hybrid as of June 2026. The rest are on-site roles based in Oregon metros.
How do I apply for design verification jobs in Oregon?
You can apply to design verification jobs in Oregon directly on Migrate Mate. Search the listings above, find roles that match your experience and preferred Oregon location, then apply to each one that fits.
See All 20 Design Verification Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Design Verification Jobs