Design Verification Jobs in California
Design Verification jobs in California are in strong and consistent demand, concentrated in the semiconductor, consumer electronics, and defense electronics sectors at seniority levels from entry-level verification engineer through principal and staff engineer. The heaviest hiring activity is in San Jose, San Diego, and Santa Clara, where companies like Qualcomm, Intel, and Apple maintain large engineering campuses. Functional verification, UVM and SystemVerilog testbench development, and formal verification are the specialties California employers request most often. Find a role that fits below and apply directly.
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Showing 5 of 144+ Design Verification jobs
INTRODUCTION
The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives. Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products? If so, come join us to do something wonderful. As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple Server SoCs.
BASIC QUALIFICATIONS
A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
- Analytical and problem-solving skills
- Verbal/written communication skills
- Effective team player with continuous learning mindset
- Willingness to balance multiple tasks
- Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process
Responsibilities
The primary responsibilities for this role will include, but are not limited to:
- Test bench development, directed/constrained random test generation in UVM
- Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
- Run RTL and gate level functional verification, debug failures, and analyze coverage
- Support mixed-signal verification using Verilog models of analog IP
MINIMUM QUALIFICATIONS
Minimum qualifications are required to be initially considered for this position.
- The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
- Relevant Work experience includes:
- IP or SoC verification experience using System Verilog/UVM
- Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
- Implementation of verification environments that include use of constrained-random stimulus
- Code/Functional Coverage analysis
- Writing System Verilog Assertions (SVA)
PREFERRED QUALIFICATIONS
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Mixed-Signal Verification
- Experience with UCIe or PCIe or I/O
JOB TYPE
Experienced Hire
SHIFT
Shift 1 (United States of America)
LOCATION
Primary Location: US, California, Santa Clara
Additional Locations: US, Oregon, Hillsboro
BUSINESS GROUP
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
POSTING STATEMENT
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
BENEFITS
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
WORK MODEL FOR THIS ROLE
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
INTRODUCTION
The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives. Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products? If so, come join us to do something wonderful. As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple Server SoCs.
BASIC QUALIFICATIONS
A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
- Analytical and problem-solving skills
- Verbal/written communication skills
- Effective team player with continuous learning mindset
- Willingness to balance multiple tasks
- Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process
Responsibilities
The primary responsibilities for this role will include, but are not limited to:
- Test bench development, directed/constrained random test generation in UVM
- Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
- Run RTL and gate level functional verification, debug failures, and analyze coverage
- Support mixed-signal verification using Verilog models of analog IP
MINIMUM QUALIFICATIONS
Minimum qualifications are required to be initially considered for this position.
- The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
- Relevant Work experience includes:
- IP or SoC verification experience using System Verilog/UVM
- Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
- Implementation of verification environments that include use of constrained-random stimulus
- Code/Functional Coverage analysis
- Writing System Verilog Assertions (SVA)
PREFERRED QUALIFICATIONS
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Mixed-Signal Verification
- Experience with UCIe or PCIe or I/O
JOB TYPE
Experienced Hire
SHIFT
Shift 1 (United States of America)
LOCATION
Primary Location: US, California, Santa Clara
Additional Locations: US, Oregon, Hillsboro
BUSINESS GROUP
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
POSTING STATEMENT
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
BENEFITS
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
WORK MODEL FOR THIS ROLE
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
See All 144+ Design Verification Jobs in California
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Find Design Verification JobsDesign Verification Jobs by City in California
Where California roles are concentrated, by current openings.
Design Verification Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Apple49
- Google15
- Broadcom9
- Qualcomm7
- Intel5
Top Industries Hiring
- Electronics & Hardware96
- Technology & Software33
- Consulting & Professional Services6
- Artificial Intelligence5
- Telecommunications4
What California Employers Look For
The qualifications that appear most often in design verification jobs across California.
- Bachelor's degree in electrical engineering, computer engineering, or a closely related field
- Proficiency in SystemVerilog and UVM for constrained-random testbench development
- Experience with industry-standard simulation tools such as VCS, Xcelium, or Questa
- Familiarity with formal verification methods and tools including JasperGold or Questa Formal
- Strong understanding of digital logic design, microarchitecture, and hardware description languages
- Experience with scripting languages such as Python or Perl for test automation and coverage analysis
Design Verification Jobs in California: Frequently Asked Questions
How do you become a design verification in California?
Most design verification roles in California require at least a bachelor's degree in electrical engineering, computer engineering, or computer science from an accredited program. There is no state-issued license specific to this role, so employers focus on demonstrated skills in SystemVerilog, UVM, and simulation tools. Many California engineers supplement their degree with coursework or projects in digital design and verification methodology, and a strong portfolio of testbench work or silicon tape-out experience is a significant advantage when applying to California semiconductor and electronics companies.
How much do design verifications make in California?
Design verifications in California earn a median of about $160,520 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $97,140 for the lowest 10% to over $225,400 for the top 10%. Pay rises with experience, specialty, and employer.
Which companies hire design verifications in California?
Employers hiring design verifications in California right now include Apple, Google, and Broadcom, based on current listings on Migrate Mate as of June 2026. California's dense concentration of semiconductor companies, fabless chip designers, and consumer electronics firms means design verification is one of the most consistently posted engineering roles across the state.
Which California cities have the most design verification jobs?
The California cities with the most design verification openings are San Jose, Santa Clara, and San Diego. This distribution reflects the Silicon Valley and Bay Area's deep concentration of semiconductor and fabless chip companies, while San Diego's strength is driven by Qualcomm's large verification organization and a cluster of wireless and defense electronics firms that have grown around it.
Are there remote design verification jobs in California?
Yes, but they're less common than in purely software-focused engineering fields, since design verification often requires access to proprietary simulation servers, lab hardware, and secure design databases. About 12% of design verification openings tied to California are remote or hybrid as of June 2026, which is lower than many tech disciplines. Roles focused on pre-silicon simulation and formal verification are the most likely to allow partial remote work, while positions involving emulation platforms or lab-based debugging typically require on-site presence.
How can I get hired as a design verification in California with little or no experience?
The most realistic entry path is applying to new-graduate or associate verification engineer programs at large California semiconductor companies, which recruit directly from California's engineering schools and regularly hire candidates whose only hands-on experience comes from coursework projects or internships. Building a public portfolio of SystemVerilog testbenches on GitHub and completing a capstone project that demonstrates UVM methodology can substitute for professional experience at many California fabless startups. Adjacent roles such as FPGA design assistant, hardware quality assurance technician, or EDA applications support engineer are also common stepping stones into full verification positions at California employers.
Where can I find and apply to design verification jobs in California?
You can find and apply to design verification jobs in California on Migrate Mate, which lists current California openings from employers actively hiring for this role. Search the listings to find roles that match your experience level, preferred metro, and specialty area, then apply directly to the ones that fit.
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