E-3 Visa Ic Design Engineer Jobs
IC design engineer roles qualify for E-3 visa sponsorship as specialty occupations requiring a bachelor's degree in electrical engineering or a closely related field. Australian engineers working on analog, digital, or mixed-signal IC design can secure two-year renewable status with no lottery and no annual cap.
Find E-3 Visa Ic Design Engineer JobsOverview
Showing 5 of 45+ Ic Design Engineer jobs
See all 45+ Ic Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Ic Design Engineer roles.
Get Access To All JobsThe application window is expected to close on: 09/30/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
As a Package Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide technical guidance, mentorship, resource coordination, and people leadership for package layout activities across advanced ASIC packaging projects.
Working closely with package leads, SI/PI teams, and the global layout organization, you will help strengthen layout engineering capability, improve methodologies and flows, and support high‑quality package implementations. This role combines technical leadership, team development, and cross‑functional collaboration in a fast‑paced and highly collaborative engineering environment.
Responsibilities:
- Lead and support the San Jose package layout team, providing technical guidance, mentorship, and day‑to‑day support to layout engineers.
- Support package layout activities for complex ASIC packaging projects, ensuring high‑quality implementation aligned with package design, SI/PI, and manufacturing requirements.
- Collaborate closely with package leads, SI/PI teams, silicon floor planning, and manufacturing partners to resolve technical and process challenges.
- Coordinate layout resource allocation, priorities, and staffing across multiple concurrent projects.
- Support optimization of package pinouts, stack‑ups, power distribution, escape routing, and high‑speed interface implementation.
- Partner with the global Package Layout Manager and other regional leaders to align methodologies, tools, best practices, and engineering standards across sites.
- Contribute to hiring, onboarding, mentoring, and development of layout engineering talent in San Jose.
- Work with vendors and contractors as needed to support project execution and delivery goals.
- Drive continuous improvement in layout methodologies, quality, and engineering efficiency.
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering or a related field with 12+ years of work experience or Master’s degree in Electrical Engineering or a related field with 8+ years of work experience or PhD in Electrical Engineering or a related field with 5+ years of work experience.
- 5+ years of experience in package layout or advanced PCB/package implementation.
- Prior experience working with high‑speed routing, power distribution networks (PDN), and package layout design principles.
- Experience with industry‑standard EDA tools for package layout and design.
Preferred Qualifications
- Experience leading or mentoring layout engineers or small technical teams.
- Proficiency with Cadence APD+ or equivalent package layout tools.
- Experience with ASIC package layout implementation, including high‑speed interfaces and complex escape routing.
- Prior experience with SI/PI considerations and collaboration with cross‑functional engineering teams.
- Experience working with vendors or outsourced layout resources.
- Experience with scripting languages such as Python, Perl, or TCL.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$210,600.00 - $350,800.00
Non-Metro New York state & Washington state:
$189,300.00 - $312,200.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
The application window is expected to close on: 09/30/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
As a Package Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide technical guidance, mentorship, resource coordination, and people leadership for package layout activities across advanced ASIC packaging projects.
Working closely with package leads, SI/PI teams, and the global layout organization, you will help strengthen layout engineering capability, improve methodologies and flows, and support high‑quality package implementations. This role combines technical leadership, team development, and cross‑functional collaboration in a fast‑paced and highly collaborative engineering environment.
Responsibilities:
- Lead and support the San Jose package layout team, providing technical guidance, mentorship, and day‑to‑day support to layout engineers.
- Support package layout activities for complex ASIC packaging projects, ensuring high‑quality implementation aligned with package design, SI/PI, and manufacturing requirements.
- Collaborate closely with package leads, SI/PI teams, silicon floor planning, and manufacturing partners to resolve technical and process challenges.
- Coordinate layout resource allocation, priorities, and staffing across multiple concurrent projects.
- Support optimization of package pinouts, stack‑ups, power distribution, escape routing, and high‑speed interface implementation.
- Partner with the global Package Layout Manager and other regional leaders to align methodologies, tools, best practices, and engineering standards across sites.
- Contribute to hiring, onboarding, mentoring, and development of layout engineering talent in San Jose.
- Work with vendors and contractors as needed to support project execution and delivery goals.
- Drive continuous improvement in layout methodologies, quality, and engineering efficiency.
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering or a related field with 12+ years of work experience or Master’s degree in Electrical Engineering or a related field with 8+ years of work experience or PhD in Electrical Engineering or a related field with 5+ years of work experience.
- 5+ years of experience in package layout or advanced PCB/package implementation.
- Prior experience working with high‑speed routing, power distribution networks (PDN), and package layout design principles.
- Experience with industry‑standard EDA tools for package layout and design.
Preferred Qualifications
- Experience leading or mentoring layout engineers or small technical teams.
- Proficiency with Cadence APD+ or equivalent package layout tools.
- Experience with ASIC package layout implementation, including high‑speed interfaces and complex escape routing.
- Prior experience with SI/PI considerations and collaboration with cross‑functional engineering teams.
- Experience working with vendors or outsourced layout resources.
- Experience with scripting languages such as Python, Perl, or TCL.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$210,600.00 - $350,800.00
Non-Metro New York state & Washington state:
$189,300.00 - $312,200.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
See all 45+ E-3 Visa Ic Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new E-3 Visa Ic Design Engineer Jobs.
Get Access To All JobsTips for Finding E-3 Visa Sponsorship as an Ic Design Engineer
Align your degree to the role
U.S. consular officers scrutinize whether your Australian engineering degree matches the IC design role specifically. A bachelor's in electrical or computer engineering supports the specialty occupation requirement; a general engineering degree may require additional documentation linking your coursework to semiconductor or VLSI design.
Target semiconductor companies with LCA history
Search the DOL's Labor Condition Application disclosure data to identify employers who have filed LCAs for IC design or related semiconductor engineering titles. Repeated LCA filings signal an employer who understands the E-3 visa process and won't need educating at the offer stage.
Use Migrate Mate to find sponsoring employers
Migrate Mate filters IC design engineer roles by E-3 visa sponsorship availability, so you're not cold-applying to employers unfamiliar with Australian-only visa categories. Use Migrate Mate's E-3 filing service to handle your LCA and visa paperwork once you have an offer.
Clarify the LCA wage level before accepting
Your employer files an LCA certifying your wage meets the prevailing wage for IC design in that location. Ask to confirm the wage level before signing your offer letter, as Level I or II classifications can fall below what you'd expect for a mid-career semiconductor engineer.
Prepare a portfolio tied to VLSI or chip tape-outs
E-3 specialty occupation denials in engineering often stem from ambiguity about whether the role genuinely requires a specific degree. A portfolio documenting tape-out projects, EDA tool proficiency, and design rule check sign-offs strengthens the employer's position during the LCA and consular application.
Book your consulate appointment early after LCA certification
Once your employer's LCA is certified by the DOL, schedule your Australian consulate appointment promptly. Sydney, Melbourne, and Perth all process E-3 applications, but appointment availability varies by location and season, and delays can push back your U.S. start date by several weeks.
E-3 Visa Ic Design Engineer: Frequently Asked Questions
How do I find IC design engineer jobs with E-3 sponsorship?
Migrate Mate is the most direct way to search IC design engineer roles where employers are already open to E-3 sponsorship. Most general job boards don't filter by visa category, so you can spend weeks applying to roles where the employer has never encountered the E-3. Migrate Mate surfaces positions matched to Australian professionals specifically, saving you that back-and-forth.
How much does it cost to get an E-3 visa?
Migrate Mate's E-3 filing service covers the entire process for $499, including the Labor Condition Application, visa document preparation, and consulate appointment guidance. Traditional immigration lawyers charge $2,000–$5,000+ for the same work. The E-3 has less paperwork than most work visas, so paying thousands for legal help is usually unnecessary.
Does IC design engineering qualify as a specialty occupation for the E-3?
Yes. IC design engineering requires a bachelor's degree or higher in electrical engineering, computer engineering, or a closely related discipline, which meets the USCIS specialty occupation definition. Roles involving analog circuit design, RTL coding, physical design, or mixed-signal verification consistently satisfy the requirement. A general engineering degree without coursework relevant to semiconductor design can create complications at the consulate, so documentation matters.
How does the E-3 visa compare to the H-1B for IC design engineers?
The E-3 is available exclusively to Australian citizens and has no lottery, no annual cap, and no waiting period tied to fiscal year registration. The H-1B visa has an 85,000-slot annual cap with a randomized lottery, meaning qualified IC design engineers are often not selected despite strong credentials. For Australians, the E-3 is a direct path that can be filed any time of year with an employer LCA.
Can I change IC design employers while on an E-3 visa?
Yes, but your new employer must file a fresh LCA before you start work with them. The E-3 is employer-specific, so you can't simply transfer status the way some other visa categories allow. You'll typically need to attend a new consulate appointment in Australia unless you pursue a change of status through USCIS while already in the U.S., which adds processing time.