Formal Verification Engineer Jobs
Formal Verification Engineer jobs are open across semiconductor, aerospace, automotive, and consumer electronics, from new-grad to principal and staff level, with specializations in formal property checking, equivalence verification, and assertion-based verification. See the openings below and apply to the ones that match your experience.
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Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure every implementation step preserves functional intent and power intent. This is a hands-on role with opportunities to own block and full-chip formal signoff and shape formal methodology across multiple product generations.
Key Responsibilities
- Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist (post-synthesis, post-DFT insertion, post-CTS, post-route), and ECO netlists.
- Develop and maintain robust equivalence setups, including handling of retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
- Debug and resolve non-equivalence and abort points efficiently, partnering with RTL, synthesis, DFT, and physical design teams to root-cause issues and converge designs to clean signoff.
- Perform static low-power verification (e.g., Conformal Low Power, VC LP) against UPF power intent, covering isolation, level shifting, retention, power switches, and always-on connectivity through implementation.
- Drive functional ECO generation and implementation using formal ECO tools (e.g., Conformal ECO, Formality ECO), minimizing patch size and physical impact late in the design cycle.
- Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required by signoff criteria.
- Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal verification status in tapeout readiness reviews.
- Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell to improve runtime, capacity, and debug productivity.
- Collaborate with EDA vendors to resolve tool issues, evaluate new capabilities, and adopt best-in-class methodology across product generations.
- Develop agentic AI flows based on latest LLM and Gen-AI capabilities.
Required Qualifications
- Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
- Proficiency with industry formal verification tools (e.g., Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa or equivalent).
- Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step impacts equivalence.
- Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.
- Working knowledge of power intent (UPF/CPF) and low-power design concepts, including isolation, level shifting, retention, and power gating.
- Familiarity with DFT structures (scan, compression, MBIST, JTAG) and their treatment in formal verification.
- Good understanding of Verilog/SystemVerilog and gate-level netlists, and ability to read and reason about RTL and synthesized logic.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Strong scripting/automation skills using Python, TCL, Perl, and/or shell.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
Preferred Qualifications
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Experience with functional ECO generation and implementation on large hierarchical designs.
- Exposure to property-based formal verification (SVA, formal apps) or netlist-level CDC/RDC signoff.
- Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 7 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$124,000.00 - $254,000.00 a yearAdditional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure every implementation step preserves functional intent and power intent. This is a hands-on role with opportunities to own block and full-chip formal signoff and shape formal methodology across multiple product generations.
Key Responsibilities
- Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist (post-synthesis, post-DFT insertion, post-CTS, post-route), and ECO netlists.
- Develop and maintain robust equivalence setups, including handling of retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
- Debug and resolve non-equivalence and abort points efficiently, partnering with RTL, synthesis, DFT, and physical design teams to root-cause issues and converge designs to clean signoff.
- Perform static low-power verification (e.g., Conformal Low Power, VC LP) against UPF power intent, covering isolation, level shifting, retention, power switches, and always-on connectivity through implementation.
- Drive functional ECO generation and implementation using formal ECO tools (e.g., Conformal ECO, Formality ECO), minimizing patch size and physical impact late in the design cycle.
- Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required by signoff criteria.
- Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal verification status in tapeout readiness reviews.
- Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell to improve runtime, capacity, and debug productivity.
- Collaborate with EDA vendors to resolve tool issues, evaluate new capabilities, and adopt best-in-class methodology across product generations.
- Develop agentic AI flows based on latest LLM and Gen-AI capabilities.
Required Qualifications
- Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
- Proficiency with industry formal verification tools (e.g., Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa or equivalent).
- Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step impacts equivalence.
- Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.
- Working knowledge of power intent (UPF/CPF) and low-power design concepts, including isolation, level shifting, retention, and power gating.
- Familiarity with DFT structures (scan, compression, MBIST, JTAG) and their treatment in formal verification.
- Good understanding of Verilog/SystemVerilog and gate-level netlists, and ability to read and reason about RTL and synthesized logic.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Strong scripting/automation skills using Python, TCL, Perl, and/or shell.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
Preferred Qualifications
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Experience with functional ECO generation and implementation on large hierarchical designs.
- Exposure to property-based formal verification (SVA, formal apps) or netlist-level CDC/RDC signoff.
- Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 7 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$124,000.00 - $254,000.00 a yearAdditional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Formal Verification Engineer Jobs by Experience Level
See All 36 Formal Verification Engineer Jobs
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Find JobsFormal Verification Engineer Job Market
Who's Hiring
Top Industries Hiring
- Technology & Software
- Electronics & Hardware
- Telecommunications
- Manufacturing
- Artificial Intelligence
What Employers Look For
The qualifications that appear most often in formal verification engineer jobs.
- Proficiency in SystemVerilog Assertions and formal property verification using commercial EDA tools
- Experience writing and debugging RTL in Verilog or SystemVerilog for complex digital designs
- Familiarity with JasperGold, VC Formal, or Questa Formal formal verification platforms
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Ability to develop and maintain formal testbench environments and verification IP
- Understanding of equivalence checking, model checking, and abstract interpretation techniques
Tips for Your Formal Verification Engineer Job Search
Tailor your resume to EDA tools
List every formal verification tool you've used, including JasperGold, Cadence Jasper, Synopsys VC Formal, and Mentor Questa Formal. Hiring managers filter resumes by tool name, so a generic 'formal methods' line won't get you past the first screen.
Highlight properties you've written
Describe the specific SVA or PSL assertions you authored, the design blocks they covered, and whether they caught real bugs. Employers want proof you can write meaningful properties, not just run a tool someone else configured.
Apply early to roles that fit
Migrate Mate lists formal verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target postings by design abstraction level
Filter openings by whether they specify RTL, gate-level, or system-level verification. Your strongest work at one abstraction level may not translate directly, so applying to roles that match your depth avoids a mismatch in the technical screen.
Prepare a proof-of-concept walkthrough
Many formal verification engineer interviews include a live session where you define the verification intent for a small design block, write assertions, and explain your coverage strategy. Practice narrating your reasoning aloud, not just the final property set.
Negotiate scope alongside compensation
Ask which design blocks you'd own, how the team splits formal versus simulation, and whether there's a path to expanding coverage methodology. These questions signal seniority and help you evaluate whether the role grows the skills you want next.
Formal Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most formal verification engineers?
Apple, Qualcomm, and Meta are hiring the most formal verification engineers right now, with openings concentrated in California, Texas, and Oregon, based on current listings on Migrate Mate as of November 2026. Semiconductor fabless companies and automotive chip divisions tend to post the highest volume of open roles.
How many formal verification engineer jobs are remote?
About 17% of formal verification engineer openings are fully remote or hybrid as of November 2026, reflecting the EDA tool-heavy nature of the work, which often requires on-site license servers or secure design environments. Methodology and verification consulting roles tend to be the most remote-friendly sub-areas.
How do you become a formal verification engineer?
Start with a strong foundation in digital logic design and RTL coding, then learn SystemVerilog Assertions through open courseware or academic projects. Get hands-on with at least one commercial formal tool, build a small property-verification portfolio on a public design, and apply for verification engineering roles where you can grow into formal methods responsibilities over time.
How do you get hired as a formal verification engineer with little experience?
Apply to digital design verification roles that include a formal component rather than pure formal positions, since most teams expect engineers to grow into the specialization. Demonstrate that you understand the difference between simulation coverage and formal proof closure, contribute to open-source RTL projects with assertion coverage, and be ready to explain a design bug you caught through property checking, even a simple one.
What does the formal verification engineer interview process look like?
Most processes include an initial technical phone screen covering RTL basics and verification concepts, followed by a take-home or live coding exercise where you write assertions for a provided design block. Final rounds typically include a panel with senior verification engineers who probe your methodology decisions, a design discussion with an RTL owner, and a conversation with an engineering manager about cross-team collaboration on coverage signoff.
Where can I find and apply to formal verification engineer jobs?
You can find and apply to formal verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Search for roles that match your tool experience and design domain, then apply directly to each listing that fits your background.
See All 36 Formal Verification Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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