Circuit Design Engineer Green Card Jobs
Circuit Design Engineer roles qualify for employment-based green card sponsorship under EB-2 or EB-3, depending on your degree level and the position's requirements. Employers file a PERM labor certification with DOL before sponsoring permanent residency, making early alignment with sponsorship-ready hardware companies essential.
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Get Access To All JobsJOB DETAILS:
JOB DESCRIPTION:
We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.
This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation. Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.
The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.
Desired traits:
- Excellent communication, documentation, and presentation skills.
- Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.
- Demonstrated leadership in cross-functional technical discussions and decision-making.
- Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving.
QUALIFICATIONS:
MINIMUM QUALIFICATIONS
Master's degree in Electrical Engineering, Electronics Engineering, or related field.
- 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.
- Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.
- Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).
- Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
- Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
- Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
- Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
PREFERRED QUALIFICATIONS
Ph.D. in Electrical Engineering, Electronics Engineering, or related field.
- 10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.
- Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.
- Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.
- Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).
- Strong understanding of signal integrity, channel modeling, and system-level link performance.
- Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.
JOB TYPE:
Experienced Hire
SHIFT:
Shift 1 (United States of America)
PRIMARY LOCATION:
US, California, Santa Clara
ADDITIONAL LOCATIONS:
US, Arizona, Phoenix
US, Oregon, Hillsboro
BUSINESS GROUP:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
POSTING STATEMENT:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
POSITION OF TRUST
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
BENEFITS
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
WORK MODEL FOR THIS ROLE
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
JOB DETAILS:
JOB DESCRIPTION:
We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.
This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation. Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.
The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.
Desired traits:
- Excellent communication, documentation, and presentation skills.
- Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.
- Demonstrated leadership in cross-functional technical discussions and decision-making.
- Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving.
QUALIFICATIONS:
MINIMUM QUALIFICATIONS
Master's degree in Electrical Engineering, Electronics Engineering, or related field.
- 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.
- Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.
- Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).
- Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
- Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
- Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
- Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
PREFERRED QUALIFICATIONS
Ph.D. in Electrical Engineering, Electronics Engineering, or related field.
- 10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.
- Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.
- Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.
- Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).
- Strong understanding of signal integrity, channel modeling, and system-level link performance.
- Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.
JOB TYPE:
Experienced Hire
SHIFT:
Shift 1 (United States of America)
PRIMARY LOCATION:
US, California, Santa Clara
ADDITIONAL LOCATIONS:
US, Arizona, Phoenix
US, Oregon, Hillsboro
BUSINESS GROUP:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
POSTING STATEMENT:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
POSITION OF TRUST
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
BENEFITS
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
WORK MODEL FOR THIS ROLE
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
See all 26+ Circuit Design Engineer jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Circuit Design Engineer roles.
Get Access To All JobsTips for Finding Green Card Sponsorship as a Circuit Design Engineer
Target employers with active PERM filing history
Semiconductor companies, defense contractors, and EDA tool vendors file PERM petitions regularly for circuit design roles. Search DOL PERM disclosure data to identify which employers have sponsored similar positions, then prioritize those in your outreach.
Use Migrate Mate to filter sponsorship-ready postings
Most job boards mix sponsored and non-sponsored listings with no way to tell them apart. Migrate Mate lets you filter specifically for employers with green card sponsorship history, saving you from applying to roles where PERM is off the table.
Verify prevailing wage before negotiating your offer
PERM locks in a wage level that your employer must meet throughout the process. Use the OFLC Wage Search to look up the prevailing wage for your SOC code and location before you accept an offer, so there are no surprises at filing.
Ask about concurrent filing during offer negotiations
Once your PERM is certified, your employer files the I-140 with USCIS. If your priority date is current, you can file I-485 adjustment of status concurrently, cutting total processing time. Confirm your future employer's attorney handles concurrent filings.
Circuit Design Engineer jobs are hiring across the US. Find yours.
Find Circuit Design Engineer JobsCircuit Design Engineer Green Card Sponsorship: Frequently Asked Questions
Does a Circuit Design Engineer role qualify for EB-2 or EB-3 sponsorship?
It depends on the position's stated requirements. Roles requiring a master's degree or equivalent advanced expertise in analog, mixed-signal, or RF design typically qualify under EB-2. Roles requiring only a bachelor's degree in electrical engineering file under EB-3 as a professional. Your employer's immigration attorney determines the classification when drafting the PERM job description.
How does green card sponsorship differ from H-1B for circuit design engineers?
H-1B is temporary, capped at 85,000 annually, and subject to a lottery. PERM-based green card sponsorship has no annual cap at the petition level and results in permanent residency. The tradeoff is time: PERM labor certification typically takes one to two years before you even reach the I-140 stage, whereas H-1B status can begin in months.
What does the PERM process look like for an engineering role like this?
Your employer conducts a supervised recruitment campaign to prove no qualified U.S. workers were available for your specific role. For circuit design positions, that often includes posting on engineering job boards and documenting each application reviewed. DOL then certifies or audits the application. Audits are common for specialized roles, so thorough documentation from day one matters.
How do I find employers who actually sponsor green cards for circuit design engineers?
Migrate Mate lets you search specifically for employers with employment-based green card sponsorship history, so you're not guessing which companies will sponsor. Focus your search on semiconductor firms, aerospace and defense primes, and integrated circuit design houses, as these sectors file PERM petitions for circuit design roles most consistently.
Can I switch jobs after my employer files the PERM but before my green card is approved?
Yes, but with conditions. If your I-140 has been approved for 180 days or more and your I-485 is pending, portability rules under AC21 let you change to a same or similar role without restarting the process. Leaving before I-140 approval generally means your PERM is abandoned and your priority date is lost.
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