Remote Design Verification Engineer Jobs
Remote Design Verification Engineer jobs are in active demand across the U.S., with remote-first semiconductor companies, distributed hardware teams, and EDA software firms regularly posting open roles. Employers hiring remotely right now include ASML, K2 Space, and NVIDIA. Scan the live roles below and apply to whichever ones fit.
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Showing 5 of 7+ Remote Design Verification Engineer jobs
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
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Find JobsRemote Design Verification Engineer Job Market
Who's Hiring
Top Industries Hiring
- Technology & Software
- Electronics & Hardware
What Employers Look For
The qualifications that appear most often in remote design verification engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM-based constrained-random testbench development
- Experience with functional coverage, assertion-based verification, and coverage closure
- Familiarity with industry EDA simulation tools such as VCS, Xcelium, or Questa
- Knowledge of common on-chip protocols including AXI, PCIe, USB, or DDR
- Experience with scripting languages such as Python or Perl for verification automation
Tips for Your Remote Design Verification Engineer Job Search
Showcase your async debug process
Remote design verification employers want to see how you investigate simulation failures on your own. Document a regression triage you led, the tools you used, and how you communicated findings in writing. That evidence replaces the trust that an in-office environment builds in person.
Highlight your UVM and coverage methodology upfront
Remote hiring managers move fast. Lead your resume and any written application materials with your specific UVM experience, coverage closure numbers, and the simulators you've used, so reviewers can assess fit before a single call.
Apply early to remote roles that fit
Migrate Mate lists remote design verification engineer openings from across the U.S. in one place. Search the current listings, find roles that match your stack and seniority, and apply directly before postings fill.
Prepare for remote-style technical screens
Remote design verification interviews typically involve a shared simulation environment or take-home testbench exercise. Practice writing a constrained-random UVM sequence and explaining your coverage model choices in a written or recorded format before your first screen.
Remote Design Verification Engineer Jobs: Frequently Asked Questions
How do I get a remote design verification engineer job?
Target companies with established distributed engineering teams, particularly remote-first semiconductor IP firms, fabless chip design startups, and EDA tool vendors. Remote employers screen for proficiency in SystemVerilog, UVM, and constrained-random testbench development alongside strong written communication and the ability to run simulations and debug independently without in-person support. Demonstrating async collaboration habits and a portfolio of verification closures gives you a clear edge.
Which companies hire remote design verification engineers?
Employers currently hiring remote design verification engineers include ASML, K2 Space, and NVIDIA, per current remote listings on Migrate Mate as of November 2026. Remote openings for this role concentrate at fabless semiconductor companies, EDA software vendors, and IP licensing firms that build fully distributed engineering teams.
Can you get a remote design verification engineer job with no experience?
Yes, but remote entry-level design verification roles are limited because employers expect you to debug simulation failures and manage regression runs without in-person guidance. Fabless startups and EDA tool companies occasionally hire junior engineers remotely. Showing personal verification projects on GitHub, contributing to open-source UVM testbenches, or completing FPGA-based verification coursework helps you stand in for direct work history.
Do you need a degree for remote design verification engineer jobs?
Usually, but a bachelor's degree in electrical engineering, computer engineering, or computer science is the standard baseline rather than a strict gate. Remote employers weigh hands-on SystemVerilog and UVM skill, demonstrated simulation and coverage closure results, and the ability to work through complex bugs independently. Candidates who show real verification work, through projects, open-source contributions, or prior internships, can offset a non-traditional academic background.
Which industries hire the most remote design verification engineers?
The sectors hiring the most remote design verification engineers are Technology & Software and Electronics & Hardware, based on current remote listings on Migrate Mate as of November 2026. These sectors rely on distributed chip design and IP development workflows that make fully remote verification roles a practical choice for their engineering teams.
See All 7 Remote Design Verification Engineer Jobs
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