Design Verification Engineer Jobs
Design Verification Engineer jobs are open across semiconductor, defense, consumer electronics, and automotive industries, from new-grad to principal and staff levels, with specializations in functional verification, UVM testbench development, and formal verification. Find a role that fits below and apply directly.
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Showing 5 of 724+ Design Verification Engineer jobs
The application window is expected to close on: 07/31/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role will work onsite out of our San Jose, CA office.
Who We Are:
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Who You'll Work With:
You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.
What You'll Do:
- Maintaining existing DV environments and enhancing them
- Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop test cases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage
- Use AI tools to develop innovative methods and processes to improve quality of design verification.
Minimum Qualifications:
- Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology
- Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
- Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Prior experience with functional coverage and constrained random DV environments.
- Scripting skills: Perl and/or Python scripting
Preferred Qualifications:
- Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$183,800.00 - $303,100.00
Non-Metro New York state & Washington state:
$163,600.00 - $269,800.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
The application window is expected to close on: 07/31/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role will work onsite out of our San Jose, CA office.
Who We Are:
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Who You'll Work With:
You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.
What You'll Do:
- Maintaining existing DV environments and enhancing them
- Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop test cases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage
- Use AI tools to develop innovative methods and processes to improve quality of design verification.
Minimum Qualifications:
- Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology
- Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
- Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Prior experience with functional coverage and constrained random DV environments.
- Scripting skills: Perl and/or Python scripting
Preferred Qualifications:
- Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$183,800.00 - $303,100.00
Non-Metro New York state & Washington state:
$163,600.00 - $269,800.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
Top Cities Hiring Design Verification Engineers
Explore design verification engineer openings in the cities hiring most right now.
See All 724+ Design Verification Engineer Jobs
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Find JobsDesign Verification Engineer Job Market
Who's Hiring
- Apple165
- NVIDIA57
- Google39
- TechBiz Global29T
- Qualcomm19
Top Industries Hiring
- Electronics & Hardware355
- Technology & Software196
- Artificial Intelligence51
- Telecommunications25
- Consulting & Professional Services24
What Employers Look For
The qualifications that appear most often in design verification engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM-based constrained-random testbench development
- Experience with functional coverage, assertion-based verification, and coverage closure
- Familiarity with industry EDA simulation tools such as VCS, Xcelium, or Questa
- Knowledge of common on-chip protocols including AXI, PCIe, USB, or DDR
- Experience with scripting languages such as Python or Perl for verification automation
Tips for Your Design Verification Engineer Job Search
Tailor your resume to the stack
Design verification roles split sharply between UVM, SystemVerilog, and formal tools like Jasper or OneSpin. Call out exactly which tools and methodologies you used on each project so hiring managers don't have to guess whether your experience matches their environment.
Quantify coverage closure results
Hiring managers expect to see what you actually closed, not just that you wrote testbenches. State the coverage metrics you hit, the bug counts you surfaced, or the regression turnaround times you improved so your impact is concrete and comparable.
Filter openings by protocol and domain
A PCIe verification role demands different expertise than a RISC-V or DDR5 one. Narrow your search by the protocol or IP domain you know best so you apply to roles where your background is an immediate fit rather than a partial match.
Apply early to roles that fit
Migrate Mate lists design verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Prepare a debug walkthrough for interviews
Most design verification engineer interviews include a live or whiteboard debug scenario. Practice walking through a failing assertion or unexpected simulation waveform out loud, explaining your reasoning at each step, not just the final answer.
Negotiate around tape-out calendar timing
Design verification teams ramp hiring before tape-out and slow it after. If an offer arrives late in a project cycle, ask about the next phase roadmap and whether the role is sustaining or greenfield, since it directly affects your scope and growth.
Design Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most design verification engineers?
Apple, NVIDIA, and Google are hiring the most design verification engineers right now, with openings concentrated in California, Texas, and Massachusetts, based on current listings on Migrate Mate as of June 2026. Semiconductor IP companies and fabless chip designers tend to post the highest volumes consistently.
How many design verification engineer jobs are remote?
About 21% of design verification engineer openings are fully remote or hybrid as of June 2026, though fully on-site roles remain common at defense contractors and companies with strict IP security requirements. Roles focused on simulation, testbench development, and formal verification tend to have more remote flexibility than positions requiring lab access or hardware bring-up support.
How do you become a design verification engineer?
Start with a degree in electrical engineering, computer engineering, or computer science, then build hands-on skills in SystemVerilog and UVM through coursework, open-source projects, or internships. Learn at least one major EDA simulator and practice writing constrained-random tests with functional coverage. Internship experience at a semiconductor company, even in a related role, is one of the most effective ways to break into full verification positions.
How do you get hired as a design verification engineer with little experience?
Focus on building a public or shareable verification project using an open-source RISC-V core or similar RTL design, and document your UVM environment, coverage plan, and bug findings. Entry-level roles at smaller fabless startups or EDA tool vendors are often more accessible than positions at large chipmakers. Targeting companies that run structured graduate programs in verification also improves your odds significantly at the early-career stage.
What does the design verification engineer interview process look like?
The process typically starts with a recruiter screen followed by a technical phone interview covering SystemVerilog constructs, UVM architecture, and basic digital design concepts. A take-home or virtual coding exercise involving testbench development or assertion writing is common at the midpoint. Final rounds usually include a loop of technical interviews with engineers covering debug scenarios, coverage methodology, and protocol knowledge, plus a hiring manager conversation on project experience and team fit.
Where can I find and apply to design verification engineer jobs?
You can find and apply to design verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Find the roles that match your experience and the protocols or domains you know, then apply directly to each listing that fits.
See All 724+ Design Verification Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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