Design Verification Engineer Jobs in Santa Clara, CA
Design Verification Engineer jobs in Santa Clara are in high demand, concentrated in the Central Expressway corridor, the Innovation Way district, and the Silicon Valley Power area, across semiconductor, fabless chip design, and consumer electronics sectors. Employers hiring right now include Marvell Technology, Apple, and NVIDIA. Find a role that fits below and apply directly.
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Showing 5 of 132+ Design Verification Engineer jobs
As we continue to grow, we’re looking for a skilled Principal Design Verification Engineer to join our dynamic team and contribute to our mission of transforming business processes through technology.
This is a fantastic opportunity to join an established and well-respected organization offering tremendous career growth potential.
Job Title: Principal Design Verification Engineer
Location: Santa Clara, CA (Onsite)
Salary: $158,600 - $317,800
Bonus + RSUs
Job Summary
We are seeking an experienced Principal Design Verification Engineer to lead verification activities for complex SoC/ASIC designs. The ideal candidate will have strong expertise in SystemVerilog, UVM, and functional verification, along with a proven track record of successful SoC tape-outs.
Responsibilities
Lead Design Verification efforts for complex SoC projects.
Develop and maintain verification environments using SystemVerilog and UVM.
Create verification test plans, develop tests, and drive coverage closure.
Debug verification failures and work closely with design teams.
Develop automation tools using Python or Perl.
Support boot code verification and multi-core SoC validation.
Mentor and lead verification engineers.
Required Skills
10+ years of Design Verification experience (or MS/PhD with 5+ years).
Strong experience with SystemVerilog and UVM.
Experience with SoC/ASIC verification and successful tape-outs.
Expertise in constrained-random and coverage-driven verification.
Python or Perl scripting experience.
Experience with EDA verification tools.
Strong Linux, C++, and Object-Oriented Programming skills.
ARM Assembly experience preferred.
Education
BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field
Relocation Assistance Available
Visa Sponsorship Available
Would you like to know more about this opportunity? For immediate consideration, please send your resume to ayushi@bvteck.com or contact us at (908) 650-6382
Bright Vision Technologies, we are committed to equal employment opportunities and fostering an inclusive work environment. If you require accommodations during the recruitment process, please let us know.
Position offered by “No Fee agency.”
Equal Employment Opportunity (EEO) Statement
Bright Vision Technologies (BV Teck) is committed to equal employment opportunity (EEO) for all employees and applicants without regard to race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, genetic information, disability, veteran status, or any other protected status as defined by applicable federal, state, or local laws. This commitment extends to all aspects of employment, including recruitment, hiring, training, compensation, promotion, transfer, leaves of absence, termination, layoffs, and recall.
BV Teck expressly prohibits any form of workplace harassment or discrimination. Any improper interference with employees' ability to perform their job duties may result in disciplinary action up to and including termination of employment.
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As we continue to grow, we’re looking for a skilled Principal Design Verification Engineer to join our dynamic team and contribute to our mission of transforming business processes through technology.
This is a fantastic opportunity to join an established and well-respected organization offering tremendous career growth potential.
Job Title: Principal Design Verification Engineer
Location: Santa Clara, CA (Onsite)
Salary: $158,600 - $317,800
Bonus + RSUs
Job Summary
We are seeking an experienced Principal Design Verification Engineer to lead verification activities for complex SoC/ASIC designs. The ideal candidate will have strong expertise in SystemVerilog, UVM, and functional verification, along with a proven track record of successful SoC tape-outs.
Responsibilities
Lead Design Verification efforts for complex SoC projects.
Develop and maintain verification environments using SystemVerilog and UVM.
Create verification test plans, develop tests, and drive coverage closure.
Debug verification failures and work closely with design teams.
Develop automation tools using Python or Perl.
Support boot code verification and multi-core SoC validation.
Mentor and lead verification engineers.
Required Skills
10+ years of Design Verification experience (or MS/PhD with 5+ years).
Strong experience with SystemVerilog and UVM.
Experience with SoC/ASIC verification and successful tape-outs.
Expertise in constrained-random and coverage-driven verification.
Python or Perl scripting experience.
Experience with EDA verification tools.
Strong Linux, C++, and Object-Oriented Programming skills.
ARM Assembly experience preferred.
Education
BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field
Relocation Assistance Available
Visa Sponsorship Available
Would you like to know more about this opportunity? For immediate consideration, please send your resume to ayushi@bvteck.com or contact us at (908) 650-6382
Bright Vision Technologies, we are committed to equal employment opportunities and fostering an inclusive work environment. If you require accommodations during the recruitment process, please let us know.
Position offered by “No Fee agency.”
Equal Employment Opportunity (EEO) Statement
Bright Vision Technologies (BV Teck) is committed to equal employment opportunity (EEO) for all employees and applicants without regard to race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, genetic information, disability, veteran status, or any other protected status as defined by applicable federal, state, or local laws. This commitment extends to all aspects of employment, including recruitment, hiring, training, compensation, promotion, transfer, leaves of absence, termination, layoffs, and recall.
BV Teck expressly prohibits any form of workplace harassment or discrimination. Any improper interference with employees' ability to perform their job duties may result in disciplinary action up to and including termination of employment.
fwuMRC1gbV
See All 132+ Design Verification Engineer Jobs in Santa Clara
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Find JobsDesign Verification Engineer Job Market in Santa Clara
Who's Hiring
- Marvell Technology27
- Apple18
- NVIDIA14
- Intel Corporation14
- AMD9
Top Industries Hiring
- Electronics & Hardware41
- Technology & Software23
- Agriculture & Farming5
- Artificial Intelligence5
Design Verification Engineer Jobs in Santa Clara: Frequently Asked Questions
How do I get a design verification engineer job in Santa Clara?
Focus on Santa Clara's dense semiconductor and fabless IC ecosystem, where demand for verification engineers is highest. Targeting employers clustered along the Central Expressway corridor and around Great America Parkway gives you the strongest concentration of open roles. Hands-on experience with SystemVerilog, UVM, and functional coverage writing stands out here, as does familiarity with low-power design verification, which is a priority for many local chip teams.
Which companies hire design verification engineers in Santa Clara?
Santa Clara design verification engineer roles are posted by Marvell Technology, Apple, and NVIDIA and others right now, based on current listings on Migrate Mate as of August 2026. Santa Clara's employer base skews heavily toward semiconductor IP companies, fabless chip designers, and large integrated device manufacturers with deep verification teams on-site.
Are there remote design verification engineer jobs in Santa Clara?
Yes, though remote availability is limited because design verification work often requires access to lab hardware, internal EDA tool licenses, and tapeout infrastructure that employers keep on-site. About 61% of design verification engineer openings tied to Santa Clara are remote or hybrid as of August 2026, with hybrid arrangements most common for simulation-heavy and testbench development tasks that do not require physical lab access.
How can I get a design verification engineer job in Santa Clara with little or no experience?
The most realistic entry path in Santa Clara is landing a junior or associate verification engineer role at a mid-size fabless semiconductor company, where small team sizes mean new engineers get broader exposure faster. Targeting internship-to-hire pipelines at Santa Clara's IC design firms, building public UVM testbench projects, and pursuing roles titled verification intern or DV associate at companies near the Convention Center district can all open the door without prior industry experience.
Which industries hire the most design verification engineers in Santa Clara?
Santa Clara design verification engineer roles concentrate in Electronics & Hardware, Technology & Software, and Agriculture & Farming, based on current listings on Migrate Mate as of August 2026. Santa Clara's position as the headquarters city for dozens of semiconductor and wireless chip companies makes it one of the densest markets in the country for verification talent across both digital and mixed-signal design teams.
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