Design Verification Engineer Jobs in San Jose, CA
Design Verification Engineer jobs in San Jose are concentrated in North San Jose, the Alviso area, and the stretch of Silicon Valley along the Great America Parkway corridor, where semiconductor, fabless chip, and EDA companies cluster. Leading employers include Cisco, Sambanova, and Astera Labs. Find a role that fits below and apply directly.
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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Overview
We are looking for a Principal Design Verification Engineer with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred.
- 8 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
Required Experience
- Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
- Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
- Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
- Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
- Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.
Preferred Experience
- Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
- Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
- Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
- Experience with directed test based methodologies, cache verification and formal methods.
The base salary range is USD 185,000.00 – USD 240,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Overview
We are looking for a Principal Design Verification Engineer with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred.
- 8 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
Required Experience
- Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
- Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
- Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
- Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
- Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.
Preferred Experience
- Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
- Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
- Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
- Experience with directed test based methodologies, cache verification and formal methods.
The base salary range is USD 185,000.00 – USD 240,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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Find JobsDesign Verification Engineer Job Market in San Jose
Who's Hiring
- Cisco28
- Sambanova17S
- Astera Labs17
- Etched11
- Broadcom11
Top Industries Hiring
- Electronics & Hardware23
- Technology & Software11
- Consulting & Professional Services6
Design Verification Engineer Jobs in San Jose: Frequently Asked Questions
How do I get a design verification engineer job in San Jose?
Target the semiconductor and fabless chip companies concentrated in North San Jose and along the Great America Parkway corridor, where demand for verification talent is highest. Hands-on experience with SystemVerilog, UVM, and formal verification tools carries the most weight locally. Engineers who have worked on complex SoC or ASIC verification environments stand out in this market, so highlighting tapeout experience and coverage closure work in your resume gives you a clear edge.
Which companies hire design verification engineers in San Jose?
Companies currently hiring design verification engineers in San Jose include Cisco, Sambanova, and Astera Labs, per current listings on Migrate Mate as of November 2026. San Jose's hiring base skews heavily toward fabless semiconductor firms, EDA tool vendors, and large-scale SoC developers with established verification teams.
Are there remote design verification engineer jobs in San Jose?
Yes, but sparingly, since design verification work typically requires access to lab hardware, simulation servers, and tightly integrated engineering teams. About 16% of design verification engineer openings tied to San Jose are remote or hybrid as of November 2026, with hybrid arrangements more common than fully remote. The portions most likely to go remote are pre-silicon simulation and formal verification tasks rather than hardware-in-the-loop or lab-dependent debug work.
How can I get a design verification engineer job in San Jose with little or no experience?
The most realistic entry path in San Jose is targeting associate or junior verification engineer roles at mid-size fabless semiconductor companies in North San Jose, which tend to invest more in developing early-career engineers than large established chipmakers. Building a portfolio of UVM testbench projects, contributing to open-source hardware verification efforts, and pursuing internships at San Jose-area EDA companies like those along the North First Street corridor can open doors that formal job postings alone do not.
Which industries hire the most design verification engineers in San Jose?
Most design verification engineer openings in San Jose sit in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, per current listings on Migrate Mate as of November 2026. San Jose's position as the historic center of the semiconductor industry means those sectors generate a disproportionate share of verification demand compared to virtually any other U.S. city.
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