Design Verification Engineer Jobs in San Jose, CA
Design Verification Engineer jobs in San Jose are concentrated in North San Jose, the Alviso area, and the stretch of Silicon Valley along the Great America Parkway corridor, where semiconductor, fabless chip, and EDA companies cluster. Leading employers include AMD, Cisco, and Astera Labs. Find a role that fits below and apply directly.
Find JobsOverview
Open roles127+
Top employerAMD
Work type60% On-site
Top credentialBachelor's degree in electrical engineering
Companies hiring16
Showing 5 of 127+ Design Verification Engineer jobs
Lead Design Verification Engineer-Memory Controller
We won't show you this job again
Added 5d ago
AMD
Lead Design Verification Engineer-Memory Controller
San Jose, California
Added 5d ago
Design Verification Tech Lead- SerDes/PHY IP
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Added 1w ago
Astera Labs
Design Verification Tech Lead- SerDes/PHY IP
San Jose, California
Added 1w ago
ASIC Design Verification Eng II Full Time - United States
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Added 1w ago
Cisco
ASIC Design Verification Eng II Full Time - United States
San Jose, California
Added 1w ago
Design Verification Engineer
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Added 1w ago
Wipro
Design Verification Engineer
San Jose, California
Added 1w ago
Design Verification Architect / Director
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Added 1w ago
Cadence Design Systems
Design Verification Architect / Director
San Jose, California
Added 1w ago
Added 5d ago
Lead Design Verification Engineer-Memory Controller
AMD·San Jose, California
Job functions:
On-Site
Bachelor's degree in electrical engineering
5,001-10,000 employees
Job Description
Overview:
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
Responsibilities:
Key Responsibilities:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
This role is not eligible for visa sponsorship.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
Adaptive and Embedded Computing Group (AECG) seeks a Senior Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.
THE PERSON:
The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.
Key Responsibilities:
- Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (DDR5, LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.
- Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.
- Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
- Develop and execute comprehensive verification plans, including testbenches and test cases.
- Collaborate with design, architecture, and software teams to define and implement verification strategies.
- Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.
- Mentor and guide junior engineers, fostering a collaborative and innovative team environment.
PREFERRED EXPERIENCE:
- Require hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4), board skew and jitter modeling.
- Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.
- Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus.
- Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.
- Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.
- Experience with gate-level simulation, power-aware verification is a plus.
- Experience with silicon debug at the tester and board level, is a plus.
ACADEMIC CREDENTIALS:
- Require BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering, or Computer Science.
This is a 5 Day per week onsite role in San Jose.
This role is not eligible for visa sponsorship.
#LI-RL1
Qualifications:
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
AMD
Lead Design Verification Engineer-Memory Controller
San Jose, California
Added 5d ago5,001-10,000 employees
Job functions:
On-Site
Bachelor's degree in electrical engineering
Job Description
Overview:
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
Responsibilities:
Key Responsibilities:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
This role is not eligible for visa sponsorship.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
Adaptive and Embedded Computing Group (AECG) seeks a Senior Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.
THE PERSON:
The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.
Key Responsibilities:
- Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (DDR5, LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.
- Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.
- Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
- Develop and execute comprehensive verification plans, including testbenches and test cases.
- Collaborate with design, architecture, and software teams to define and implement verification strategies.
- Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.
- Mentor and guide junior engineers, fostering a collaborative and innovative team environment.
PREFERRED EXPERIENCE:
- Require hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4), board skew and jitter modeling.
- Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.
- Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus.
- Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.
- Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.
- Experience with gate-level simulation, power-aware verification is a plus.
- Experience with silicon debug at the tester and board level, is a plus.
ACADEMIC CREDENTIALS:
- Require BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering, or Computer Science.
This is a 5 Day per week onsite role in San Jose.
This role is not eligible for visa sponsorship.
#LI-RL1
Qualifications:
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
See All 127+ Design Verification Engineer Jobs in San Jose
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Find JobsDesign Verification Engineer Job Market in San Jose
Who's Hiring
- AMD25
- Cisco13
- Astera Labs13
- Samsung Electronics13
- Etched8
Top Industries Hiring
- Electronics & Hardware30
- Technology & Software8
- Consulting & Professional Services4
Design Verification Engineer Jobs in San Jose: Frequently Asked Questions
How do I get a design verification engineer job in San Jose?
Target the semiconductor and fabless chip companies concentrated in North San Jose and along the Great America Parkway corridor, where demand for verification talent is highest. Hands-on experience with SystemVerilog, UVM, and formal verification tools carries the most weight locally. Engineers who have worked on complex SoC or ASIC verification environments stand out in this market, so highlighting tapeout experience and coverage closure work in your resume gives you a clear edge.
Which companies hire design verification engineers in San Jose?
Companies currently hiring design verification engineers in San Jose include AMD, Cisco, and Astera Labs, per current listings on Migrate Mate as of September 2026. San Jose's hiring base skews heavily toward fabless semiconductor firms, EDA tool vendors, and large-scale SoC developers with established verification teams.
Are there remote design verification engineer jobs in San Jose?
Yes, but sparingly, since design verification work typically requires access to lab hardware, simulation servers, and tightly integrated engineering teams. About 40% of design verification engineer openings tied to San Jose are remote or hybrid as of September 2026, with hybrid arrangements more common than fully remote. The portions most likely to go remote are pre-silicon simulation and formal verification tasks rather than hardware-in-the-loop or lab-dependent debug work.
How can I get a design verification engineer job in San Jose with little or no experience?
The most realistic entry path in San Jose is targeting associate or junior verification engineer roles at mid-size fabless semiconductor companies in North San Jose, which tend to invest more in developing early-career engineers than large established chipmakers. Building a portfolio of UVM testbench projects, contributing to open-source hardware verification efforts, and pursuing internships at San Jose-area EDA companies like those along the North First Street corridor can open doors that formal job postings alone do not.
Which industries hire the most design verification engineers in San Jose?
Most design verification engineer openings in San Jose sit in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, per current listings on Migrate Mate as of September 2026. San Jose's position as the historic center of the semiconductor industry means those sectors generate a disproportionate share of verification demand compared to virtually any other U.S. city.
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See All 127+ Design Verification Engineer Jobs in San Jose
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